TC90101FG 查看數據表（PDF） - Toshiba
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TC90101FG Datasheet PDF : 36 Pages
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TC90101FG
３．Terminals discription
Piｎ
Piｎ
No Name
1 VREFDA
2 VDDPLL
3 PLLIN
4 VCOFIL
5 VSSPLL
6 VDDXO
7 XOIN
8 XOOUT
9 VSSXO
10 TDIO9
11 TDIO8
12 TDIO7
13 TDIO6
14 TDIO5
15 DVDD1
16 TDIO4
17 TDIO3
18 TDIO2
19 DVSS1
20 TDIO1
21 TDIO0
22 TDCLK
23 VDDIO3
24 BUSSEL
25 RESET
26 SDA
27 SCL
28 TESTM1
29 TESTM2
30 TESTM3
31 TESTM4
32 DVDD2
33 CSYNCIN
34 DVSS2
35 YOUT9
36 YOUT8
37 YOUT7
38 YOUT6
39 DVDD3
40 YOUT5
41 YOUT4
42 DVSS3
43 YOUT3
44 YOUT2
45 VSSIO1
46 YOUT1
47 YOUT0
48 CKOUT
49 VDDIO1
50 TESTM5
Function
（ ）：Condition at normal operation
Durable I/O
ｖoltage
(V)
The reference voltage terminal of DAC
2.5
Power supply for X8 PLL circuit
2.5
Input terminal of X8 PLL circuit
2.5
Filter terminal for X8 PLL circuit
2.5
GND for X8 PLL circuit
0
Power supply for X’ tal OSC circuit
3.3
X’ tal OSC circuit input terminal
3.3
X’ tal OSC circuit output terminal
3.3
GND for X’ tal OSC circuit
0
3.3
3.3
Terminal for Test mode
3.3
（Normaly Open）
3.3
3.3
Power supply for Logic circuit
1.5
3.3
Terminal for Test mode
3.3
（Normaly Open）
3.3
GND for Logic circuit
0
3.3
Terminal for Test mode
3.3
（Normaly Open）
3.3
Power supply for I/O
3.3
IICBUS slave address selection(L:B0､Hi:B2)
3.3
Reset terminal (Low :Reset Hi :normal)
3.3
ＩＩＣ ＳＤＡ terminal (5V input possible）
5
ＩＩＣ ＳＣＬ terminal (5V input possible)
5
3.3
Terminal for Test mode
3.3
（Normaly connect to GND）
3.3
3.3
Power supply for Logic circuit
1.5
External composite Sync signal input
5
（In case not use external CSYNC, conect to ＧＮＤ）
GND for Logic circuit
0
Digital video port output 9 （MSB）
3.3
（656/ 601 mode：YCbCr, 601：Y）
Digital video port output 8
3.3
Digital video port output 7
3.3
Digital video port output 6
3.3
Power supply for Logic circuit
1.5
Digital video port output 5
3.3
Digital video port output 4
3.3
GND for Logic circuit
0
Digital video port output 3
3.3
Digital video port output 2
3.3
GND for I/O
0
Digital video port output 1
3.3
(In case 8bit output mode : fixed to Low)
Digital video port output 0
3.3
(In case 8bit output mode : fixed to Low)
System Clock output terminal for digital video signal output. 3.3
656 : 27MHz 601 : 13.5MHz
Power supply for I/O
3.3
Terminal for Test mode（Normaly connect to GND）
3.3
Bypass
VDD
IN
Bypass
GND
VDD
IN
OUT
GND
I/O
I/O
I/O
I/O
I/O
VDD
I/O
I/O
I/O
GND
I/O
I/O
IN
VDD
IN
IN
I/O
IN
IN
IN
IN
IN
VDD
IN
GND
OUT
OUT
OUT
OUT
VDD
OUT
OUT
GND
OUT
OUT
GND
OUT
OUT
OUT
VDD
IN
Circuit
(Analog or Digital)
Analog
Digital
DC at
normal
Oparation
（Ｖ）
1.5
2.5
1.25
1.2
0
3.3
-
-
0
-
-
-
-
-
1.5
-
-
-
0
-
-
-
3.3
-
3.3
-
-
0
0
0
0
1.5
0
0
-
-
-
-
1.5
-
-
0
-
-
0
-
-
-
3.3
0
Analog signal
Amplitude
（Vp-p）
-
-
0.5〜
VDDPLL*0.8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Feb./2005
3
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