GS882Z18B-66 查看數據表（PDF） - Giga Semiconductor

零件编号

产品描述 (功能)

比赛名单

GS882Z18B-66

8Mb Pipelined and Flow Through Synchronous NBT SRAMs

Giga Semiconductor 

GS882Z18/36 BGA Pin Description

Pin Location

U2

U3

U5

U4

J2, C4, J4, R4, J6

D3, E3, F3, H3, K3, M3, N3, P3, D5,

E5, F5, H5, K5, M5, N5, P5

A1, F1, J1, M1, U1, A7, F7, J7, M7,

U7

Symbol

TMS

TDI

TDO

TCK

VDD

VSS

VDDQ

Type

I

I

O

I

I

I

I

Preliminary.

GS882Z18/36B-11/100/80/66

Description

Scan Test Mode Select

Scan Test Data In

Scan Test Data Out

Scan Test Clock

Core power supply

I/O and Core Ground

Output driver power supply

BPR2000.002.14

Functional Details

Clocking

Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to

suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.

Pipeline Mode Read and Write Operations

All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle

read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device

activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable

inputs will deactivate the device.

Function

Read

Write Byte “a”

Write Byte “b”

Write Byte “c”

Write Byte “d”

Write all Bytes

Write Abort/NOP

W BA

BB

BC

BD

HX X X X

LL HHH

LH

L

H

H

LH H L H

LH

H

H

L

LL

L

L

L

LH H H H

Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted Low, all three

chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address

presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control

logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At

the next rising edge of clock the read data is allowed to propagate through the output register and onto the Output pins.

Write operation occurs when the RAM is selected, CKE is active and the Write input is sampled low at the rising edge of clock.

Rev: 1.15 6/2001

5/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

© 1998, Giga Semiconductor, Inc.

Share Link: