PCLK_IN
DATA_OUT[19:10]
(LUMA)
WEN
WORD503 WORD504 WORD505 WORD506 WORD507 WORD508
(Low)
R_CLK
FF_STA[2:0]
011
(Ready)
100
(Half Full)
Fig. 13 FIFO Ready to Half Full Write Timing
PCLK_IN
DATA_OUT[19:10]
(LUMA)
WEN
WORD983 WORD984 WORD985 WORD986 WORD987 WORD988
(Low)
R_CLK
FF_STA[2:0]
100
(Half Full)
101
(Almost Full)
Fig. 14 FIFO Half Full to Almost Full Write Timing
PCLK_IN
DATA_OUT[19:10]
(LUMA)
WEN
WORD
1016
WORD
1017
WORD
1018
WORD
1019
WORD
1020
WORD
1021
WORD
1022
R_CLK
FF_STA[2:0]
101
(Almost Full)
110
(Full)
111
(Write Error)
110
(Full)
Fig. 15 FIFO Almost Full to Full to Write Error Timing
PCLK_IN
R_CLK
FFRST
REN/WEN
At least 5 cycles of slowest clock
High for at least 1 cycle
after FFRST toggles
Fig. 16 Recommended External FIFO Reset Process
15
GENNUM CORPORATION
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