GS88237BB-250V 查看數據表（PDF） - Giga Semiconductor

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GS88237BB-250V

256K x 36 9Mb SCD/DCD Sync Burst SRAM

Giga Semiconductor 

GS88237BB/D-xxxV

JTAG Port Recommended Operating Conditions and DC Characteristics (1.8/2.5 V Version)

Parameter

Symbol

Min.

Max.

Unit Notes

1.8 V Test Port Input Low Voltage

VILJ1

–0.3

0.3 * VDD1

V

1

2.5 V Test Port Input Low Voltage

VILJ2

–0.3

0.3 * VDD2

V

1

1.8 V Test Port Input High Voltage

VIHJ1

0.6 * VDD1

VDD1 +0.3

V

1

2.5 V Test Port Input High Voltage

VIHJ2

0.6 * VDD2

VDD2 +0.3

V

1

TMS, TCK and TDI Input Leakage Current

IINHJ

–300

1

uA

2

TMS, TCK and TDI Input Leakage Current

IINLJ

–1

100

uA

3

TDO Output Leakage Current

IOLJ

–1

1

uA

4

Test Port Output High Voltage

VOHJ

1.7

—

V 5, 6

Test Port Output Low Voltage

Test Port Output CMOS High

VOLJ

—

0.4

VOHJC VDDQ – 100 mV

—

V 5, 7

V 5, 8

Test Port Output CMOS Low

VOLJC

—

100 mV

V 5, 9

Notes:

1. Input Under/overshoot voltage must be –2 V < Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.

2. VILJ ≤ VIN ≤ VDDn

3. 0 V ≤ VIN ≤ VILJn

4. Output Disable, VOUT = 0 to VDDn

5. The TDO output driver is served by the VDDQ supply.

6. IOHJ = –4 mA

7. IOLJ = + 4 mA

8. IOHJC = –100 uA

9. IOLJC = +100 uA

JTAG Port AC Test Conditions

Parameter

Conditions

Input high level

VDD – 0.2 V

Input low level

0.2 V

Input slew rate

1 V/ns

Input reference level

VDDQ/2

Output reference level

VDDQ/2

Notes:

1. Include scope and jig capacitance.

2. Test conditions as shown unless otherwise noted.

JTAG Port AC Test Load

DQ

50Ω

30pF*

VDDQ/2

* Distributed Test Jig Capacitance

Rev: 1.04 6/2006

23/28

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 2003, GSI Technology

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