V43648S04VTG-10PC 查看數據表（PDF） - Mosel Vitelic, Corp
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V43648S04VTG-10PC Datasheet PDF : 12 Pages
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MOSEL VITELIC
SPD-Table: (Continued)
Byte
Number Function Described
30
Minimum RAS Pulse Width tRAS
31
Module Bank Density (Per Bank)
32
SDRAM Input Setup Time
33
SDRAM Input Hold Time
34
SDRAM Data Input Setup Time
35
SDRAM Data Input Hold Time
36-61 Superset Information (May be used in Future)
62
SPD Revision
63
Checksum for Bytes 0 - 62
64
Manufacturer’s JEDEC ID Code
65–71 *Manufacturer’s JEDEC ID Code (cont.)
72
Manufacturing location
73–90 Module Part Number (ASCII)
91
*PCB Identification Code
92
*Identification Code (cont.)
93
*Assembly Manufacturing Date (year)
94
*Assembly Manufacturing Date (week)
95
*Assembly Serial Number (LSB)
96
*Assembly Serial Number
97
*Assembly Serial Number
98
*Assembly Serial Number (MSB)
99–125 Reserved
126
Maximum Frequency Specification
127
100 MHz Support Details
128+ Unused Storage Location
V43648S04V(C)TG-10PC
SPD Entry Value
50 ns
64 MByte
2 ns
1 ns
2 ns
1 ns
Revision 1.2
Mosel Vitelic
US=1 Taiwan=2
V43648S04VCTG-10PC
Hex Value
100 MHz
-10PC
32
10
20
10
20
10
00
12
FD
40
00
01
56
yy
ww
00
100 MHz
64
85
00
Notes:
1. Bytes 91–92 are the current PCB revision level for the board used in the module build. (Intel PC100 board revision
level)
2. Bytes 93–94 are the binary coded year, byte 93 (00–64hex) and binary coded week, byte 94 (01–34hex).
3. Ass embly Serial Number, bytes 95–98 is an incrementing hex count in (LSB to MSB).
4. Values in this byte or bytes are to be programmed to 00h.
V43648S04V(C)TG-10PC Rev. 1.1 June 2000
5
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