V54C316162VC-55 查看數據表（PDF） - Mosel Vitelic, Corp
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V54C316162VC-55
200/183/166/143 MHz 3.3 VOLT, 2K REFRESH ULTRA HIGH PERFORMANCE 1M X 16 SDRAM 2 BANKS X 512Kbit X 16
Mosel Vitelic, Corp
V54C316162VC-55 Datasheet PDF : 22 Pages
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MOSEL VITELIC
V54C316162VC
AC Characteristics (1,2,3)
TA = 0 to 70°C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns
Limit Values
-5
-55
-6
-7
# Symbol Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Clock and Clock Enable
tCK
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
5
–
5.5
–
6
–
7
–
ns
10
–
10
–
10
–
10
–
ns
tCK
Clock Frequency
CAS Latency = 3
CAS Latency = 2
–
200
–
183
–
166
–
143 MHz
–
100
–
100
–
100
–
100 MHz
tAC
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
–
5
–
5.3
–
5.5
–
5.5
ns
2
–
7
–
7
–
7
–
7
ns
3
tCH
Clock High Pulse Width
tCL
Clock Low Pulse Width
tT
Transition time
Setup and Hold Times
2.5
–
2.5
–
2.5
–
2.5
–
ns
2.5
–
2.5
–
2.5
–
2.5
–
ns
1
10
1
10
1
10
1
10
ns
tCMDS Command Setup Time
tAS
Address Setup Time
tDS
Data In Setup Time
tCKS
CKE Setup Time
tCMDH Command Hold Time
tAH
Address Hold Time
tDH
Data In Hold Time
tCKH
CKE Hold Time
Common Parameters
2
–
2
–
2
–
2
–
ns
4
2
–
2
–
2
–
2
–
ns
4
2
–
2
–
2
–
2
–
ns
4
2
–
2
–
2
–
2
–
ns
4
1
–
1
–
1
–
1
–
ns
4
1
–
1
–
1
–
1
–
ns
4
1
–
1
–
1
–
1
–
ns
4
1
–
1
–
1
–
1
–
ns
4
tRCD
Row to Column Delay Time
15
–
16.5
–
18
–
18
–
ns
5
tRAS
Row Active Time
40 100K 45 100K 48 100K 48 100K
ns
5
tRC
Row Cycle Time
60
–
63
–
66
–
70
–
ns
5
tRP
Row Precharge Time
15
–
17
–
18
–
21
–
ns
5
tRRD
Activate(a) to Activate(b) Com-
10
–
11
–
12
–
14
–
ns
5
mand
period
tCCD
CAS(a) to CAS(b) Command pe- 1
–
1
–
1
–
1
–
CLK
riod
tRCS
Mode Register Set-up time
10
–
11
–
12
–
14
–
ns
tSB
Power Down Mode Entry Time
0
5
0
5.5
0
6
0
7
ns
tCDL
Last data in to new column ad-
5
–
5.5
–
6
–
7
–
ns
dress delay
V54C316162VC Rev. 1.4 December 2001
10
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