AD9144 查看數據表（PDF） - Analog Devices

零件编号

产品描述 (功能)

比赛名单

AD9144

Quad, 16-Bit, 2.8 GSPS, TxDAC+® Digital-to-Analog Converter

Analog Devices 

Data Sheet

AD9144

Parameter

SDO to SCLK

Data Valid Window

CS to SCLK

Setup Time

Hold Time

Symbol Test Conditions/Comments

tDV

tSCS

tHCS

1 See Table 3 for detailed specifications for DAC update rate conditions.

2 Maximum speed for 1× interpolation is limited by the JESD interface. See Table 4 for details.

3 Maximum speed for 2× interpolation is limited by the JESD interface. See Table 4 for details.

4 See Table 4 for detailed specifications for JESD speed conditions.

5 K, F, and S are JESD204B transport layer parameters. See Table 44 for the full definitions.

6 See Table 5 for detailed specifications for SYSREF to DAC clock timing conditions.

Min

Typ Max

25

5

2

Unit

ns

ns

ns

MAXIMUM DAC UPDATE RATE SPEED SPECIFICATIONS BY SUPPLY

AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,

TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted.

Table 3.

Parameter

MAXIMUM DAC UPDATE RATE

Test Conditions/Comments

DVDD12, CVDD12 = 1.2 V ± 5%

DVDD12, CVDD12 = 1.2 V ± 2%

DVDD12, CVDD12 = 1.3 V ± 2%

Min

Typ

Max

Unit

2.23

GSPS

2.41

GSPS

2.80

GSPS

JESD204B SERIAL INTERFACE SPEED SPECIFICATIONS

AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,

TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted.

Table 4.

Parameter

HALF RATE

FULL RATE

OVERSAMPLING

Test Conditions/Comments

SVDD12 = 1.2 V ± 5%

SVDD12 = 1.2 V ±2%

SVDD12 = 1.3 V ± 2%

SVDD12 = 1.2 V ± 5%

SVDD12 = 1.2 V ± 2%

SVDD12 = 1.3 V ± 2%

SVDD12 = 1.2 V ± 5%

SVDD12 = 1.2 V ± 2%

SVDD12 = 1.3 V ± 2%

Min

Typ

Max

Unit

5.75

11.4

Gbps

5.75

12.0

Gbps

5.75

12.4

Gbps

2.88

5.98

Gbps

2.88

6.06

Gbps

2.88

6.2

Gbps

1.44

3.0

Gbps

1.44

3.04

Gbps

1.44

3.1

Gbps

Rev. B | Page 7 of 125

Share Link: