V61C518256-12R 查看數據表（PDF） - Mosel Vitelic, Corp

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V61C518256-12R

32K X 8 HIGH SPEED STATIC RAM

Mosel Vitelic, Corp 

MOSEL VITELIC

Switching Waveforms (Write Cycle)

Write Cycle 1 (WE Controlled)(4)

ADDRESS

CE

WE

OUTPUT

INPUT

tAS

tWHZ(3)

tWC

tCW(6)

tAW

tWP(1)

tDW

V61C518256

tAH(2)

tDH

518256-11

Write Cycle 2 (CE Controlled)(4)

ADDRESS

tAS

CE

WE

tWC

tCW(6)

tAW

tAH(2)

Hi-Z

OUTPUT

INPUT

tDW

tDH

(5)

518256-12

NOTES:

1. The internal write time of the memory is defined by the overlap of CE active and WE low. Both signals must be active to initiate and

any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second

transition edge of the signal that terminates the write.

2. tAH is measured from the earlier of CE or WE going HIGH.

3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.

4. OE = VIL or VIH. However it is recommended to keep OE at VIH during write cycle to avoid bus contention.

5. If CE is LOW during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must

not be applied to them.

6. tCW is measured from CE going LOW to the end of write.

V61C518256 Rev. 0.3 July 1998

8

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