SRK2000DTR(2012) 查看數據表（PDF） - STMicroelectronics

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SRK2000DTR
(Rev.:2012)

Synchronous rectifier smart driver for LLC resonant converters

STMicroelectronics 

SRK2000

1

Pin description

Figure 2. Pin configuration

SGND 1

EN 2

DVS1 3

DVS2 4

8 Vcc

7 GD1

6 PGND

5 GD2

Pin description

Table 2. Pin description

n.

Name

Function

Signal ground. Return of the bias current of the device and 0 V reference for

1

SGND drain-to-source voltage monitors of both sections. Route this pin directly to

PGND.

Drain voltage threshold setting for synchronous rectifier MOSFET turn-off. UVLO

threshold programming. This pin is typically biased by either a pull-up resistor

2

EN connected to Vcc or by a resistor divider sensing Vcc. Pulling the pin to ground

disables the gate driver outputs GD1 and GD2 and can therefore be used also

as Enable input.

Drain voltage sensing for sections 1 and 2. These pins are to be connected to

the respective drain terminals of the corresponding synchronous rectifier

3

DVS1 MOSFET via limiting resistors. When the voltage on either pin goes negative,

the corresponding synchronous rectifier MOSFET is switched on; as its

4

DVS2 (negative) voltage exceeds a threshold defined by the EN pin, the MOSFET is

switched off. An internal logic rejects switching noise, however, extreme care in

the proper routing of the drain connection is recommended.

Gate driver output for sections 2 and 1. Each totem pole output stage is able to

5

GD2 drive Power MOSFETs with a peak current of 1 A source and 3.5 A sink. The

7

GD1 high-level voltage of these pins is clamped at about 12 V to avoid excessive gate

voltages in case the device is supplied with a high Vcc.

Power ground. Return for gate-drive currents. Route this pin to the common

6

PGND point where the source terminals of both synchronous rectifier MOSFETs are

connected.

Supply voltage of the device. A small bypass capacitor (0.1 µF typ.) to SGND,

located as close to the IC’s pins as possible, may be useful to obtain a clean

8

Vcc supply voltage for the internal control circuitry. A similar bypass capacitor to

PGND, again located as close to the IC’s pins as possible, may be an effective

energy buffer for the pulsed gate-drive currents.

Doc ID 17811 Rev 2

3/17

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