MX7672(2012) 查看數據表（PDF） - Maxim Integrated
零件编号
产品描述 (功能)
比赛名单
MX7672 Datasheet PDF : 14 Pages
| |||
MX7672
High-Speed 12-Bit ADC With External
Reference Input Part
ROM Mode
Digital noise is generated in the ADC when RD or CS
go high, and the output data drivers are disabled after a
conversion is started. This noise will feed into the ADC
comparator and cause large errors if it coincides with the
time the SAR is latching a bit decision. To avoid this prob-
lem, RD and CS should be active for less than one clock
cycle. In other words, the RD and CS low pulse should
be less than 250ns for the MX7672_ _03, 400ns for the
MX7672_ _05, and 1µs for the MX7672_ _10. If this can-
not be done, the RD or CS signal must go high at a rising
edge of CLKIN, since the comparator output is always
latched at falling edges of CLKIN.
Physical Layout
For the best system performance, PCBs should be used
for the MX7672; wire-wrap boards are not recommended.
Separate the digital-analog-signal lines as much as pos-
sible in the board layout. Do not run analog and digital
lines parallel to each other or digital lines underneath the
MX7672 package.
Grounding
Figure 11 shows the recommended system ground con-
nections. Establish a single-point analog ground (star
ground), separate from the logic ground, at AGND of the
MX7672. Connect all other analog grounds and DGND of
the MX7672 to this star ground (no other digital grounds
should be connected to this point). For noise-free opera-
tion of the ADC, use a low-impedance ground return to the
power supply from this star ground.
Power-Supply Bypassing
The ADC’s high-speed comparator is sensitive to high
frequency noise in the VDD and VSS power supplies.
These supplies should be bypassed to the analog star
ground with 0.1µF and 10µF bypass capacitors with
minimum lead length for supply noise rejection. If the +5V
power supply is very noisy, a small (10Ω to 20Ω) resistor
can be connected (Figure 11) to filter external noise.
Driving the Analog Input
The input signal leads to AIN and the input return leads to
AGND should be as short as possible to minimize input noise
coupling. Use shielded cables if the leads must be long.
The input impedance at each AIN is typically 5kΩ. The
amplifier driving AIN must have low enough DC output
impedance for low gain error. Furthermore, low AC output
impedance is needed since the analog input current is
modulated at the clock rate during a conversion (up to
4MHz for MX7672_ _03, 2.5MHz for MX7672_ _05, or
1.25MHz for the MX7672_ _10). The output impedance of
the driving amplifier is equal to its open-loop output imped-
ance divided by the loop gain at the frequency of interest.
MX7672_ _05/10 - The MX7672_ _05/10 maximum clock
rate of 2.5MHz makes it possible to drive AIN with ampli-
fiers like the OP42, AD711 or a Maxim OP27. A MAX400
or a Maxim OP07 can also be used up to 1.25MHz clock
rate.
MX7672_ _03 - The MX7672_ _03, with a maximum 4MHz
clock rate, might exhibit settling problems with the above
amplifiers. An LF356, LF400, or LT1056 can be used to
drive the input. Alternatively, an emitter follower buffer
inside the feedback loop of a Maxim OP27, an OP42, or
an AD711 improves high-frequency output impedance.
Reference Input
VREF connects to an external -5V source. This may be
either a precision negative reference, a positive reference
(such as the MX584) connected as a two-terminal device
to provide -5V (Figure 16), or an existing system reference.
The allowed input range at REFIN is -5.1V to -4.9V. VREF
(and AIN2 in bipolar input operation) should be bypassed
to ground with a 10µF electrolytic capacitor in parallel with
a 0.1µF ceramic capacitor.
If the external reference is biased from a power supply
other than VSS, care must be taken to ensure that VSS
is applied to the ADC before VREF. If supply sequencing
is uncertain, connect a diode between VSS and VREF, as
shown in Flgure 12. No diode is needed if the reference
source is powered from the same supply as VSS.
MX7672 to Sample-and-Hold Interface
The analog input to the ADC must be stable to within
1/2 LSB during the entire conversion for specified 12-bit
accuracy. This limits the input-signal bandwidth to less
than 6Hz for sinusoidal inputs, even when using the faster
MX7672_ _03. A sample-and-hold should be used for
higher bandwidth signals.
The BUSY output from the MX7672 may be used to
provide the TRACK/HOLD signal to the sample-and-hold
amplifier. However, since the ADC’s DAC is switched at
approximately the same time as the BUSY signal goes
low, sample-and-hold transients caused by DAC switch-
ing may result in code-dependent errors due to sample-
and-hold aperture delay. Adding a NAND (inverted AND)
gate ensures that the sample-and-hold is switched to the
hold mode BEFORE any disturbances occur (Figures 13
and 14). The NAND gate solution works only if the width
of the RD pulse is wider than the RD to BUSY delay in
the MX7672. If this is not the case, use a flip-flop, which
is set by the falling edge of RD and reset by the rising
edge of BUSY.
www.maximintegrated.com
Maxim Integrated │ 8
Share Link: 