IDT7024S35F 查看數據表（PDF） - Integrated Device Technology

零件编号

产品描述 (功能)

比赛名单

IDT7024S35F

HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT7024S/L

HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND BUSY (M/S = VIH)(2,4,5)

tWC

ADDR"A"

W R/ "A"

MATCH

tWP

tDW

tDH

DATAIN "A"

tAPS (1)

VALID

ADDR"B"

BUSY"B"

tBAA

MATCH

tBDA

tBDD

tWDD

DATAOUT "B"

VALID

tDDD (3)

NOTES:

1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).

2. CEL = CER = VIL.

3. OE = VIL for the reading port.

4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.

5. All timing is the same for both left and right ports. Port "A" may be either the left or right Port. Port "B" is the port opposite from port "A".

2740 drw 13

TIMING WAVEFORM OF WRITE WITH BUSY

W R/ "A"

BUSY"B"

W R/ "B"

tWP

tWB( 3 )

(2)

NOTES:

1. tWH must be met for both BUSY input (slave) and output (master).

2. Busy is asserted on port "B" Blocking R/W"B", until BUSY"B" goes High.

3. tWB is only for the Slave Version.

tWH ( 1 )

2740 drw 14

6.15

13

Share Link: