IDT7024S15PFB 查看數據表（PDF） - Integrated Device Technology
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IDT7024S15PFB Datasheet PDF : 20 Pages
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IDT7024S/L
HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF INTERRUPT TIMING(1)
ADDR"A"
CE"A"
tAS(3)
tWC
INTERRUPT SET ADDRESS(2)
tWR(4)
W R/ "A"
INT"B"
ADDR"B"
CE"B"
tINS(3)
tAS (3)
tRC
INTERRUPT CLEAR ADDRESS(2)
2740 drw 17
OE"B"
INT"B"
tINR(3)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt truth table.
3. Timing depends on which enable signal ( CE or R/W ) is asserted last.
4. Timing depends on which enable signal ( CE or R/W ) is de-asserted first.
2740 drw 18
TRUTH TABLES
TRUTH TABLE III — INTERRUPT FLAG(1,4)
Left Port
R/WL
CEL
OEL A11L-A0L INTL
L
L
X
FFF
X
X
X
X
X
X
X
X
X
X
L(3)
X
L
L
FFE H(2)
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTR and INTL must be initialized at power-up.
R/WR
X
X
L
X
Right Port
CER
X
L
OER
X
L
A11R-A0R
X
FFF
INTR
L(2)
H(3)
L
X
FFE
X
X
X
X
X
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
Reset Left INTL Flag
2740 tbl 17
6.15
15
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