54S416T
SDRAM
1. GENERAL DESCRIPTION
54S416T is a high-speed synchronous dynamic random access memory (SDRAM), organized as
1M words x 4 banks x 16 bits. Using pipelined architecture.
54S416T delivers a data bandwidth of up to 400M bytes per second (-5). For different application,
54S416T is sorted into the following speed grades: -5, -6, -7. The -5 parts can run up to 200
MHz/CL3. The -6 parts can run up to 166 MHz/CL3. The -7 parts can run up to 143 MHz/CL3. For
handheld device application.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. 50S416T is ideal for main memory in
high performance applications.
2. FEATURES
• 3.3V ±0.3V power supply
• 1048576 words x 4 banks x 16 bits organization
• Burst read,single write operation
• CAS latency: 2 and 3
• Burst Length: 1, 2, 4, 8, and full page
• Sequential and Interleave burst
• Byte data controlled by DQM
• Power-down Mode
• Auto-precharge and controlled precharge
• 4K refresh cycles/64 mS
• Interface: LVTTL
• Packaged in TSOP II 54-pin, 400 mil - 0.80
3. AVAILABLE PART NUMBER
PART NUMBER
SPEED (CL = 3)
54S416T-5
54S416T-6
54S416T-7
200 MHz
166 MHz
143 MHz
SELF REFRESH
CURRENT (MAX.)
1 mA
1 mA
1 mA
OPERATING
TEMPERATURE
0° C − 70° C
0° C − 70° C
0° C − 70° C
* All specs and applications shown above subject to change without prior notice.
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Rev 1.0 Aug.21,2002