IDT7027L(2018) 查看數據表（PDF） - Integrated Device Technology
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IDT7027L Datasheet PDF : 20 Pages
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IDT7027S/L
High-Speed 32K x 16 Dual-Port Static RAM
Waveform of Interrupt Timing(1,5)
ADDR"A"
CE"A"
tAS (3)
tWC
INTERRUPT SET ADDRESS (2)
Industrial and Commercial Temperature Ranges
tWR (4)
R/W"A"
INT"B"
tINS (3)
3199 drw 15
ADDR"B"
CE"B"
tAS (3)
tRC
INTERRUPT CLEAR ADDRESS (2)
OE"B"
INT"B"
tINR(3)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See the Interrupt Truth Table IV.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
5. Refer to Chip Enable Truth Table.
3199 drw 16
Truth Table IV — Interrupt Flag(1,4)
Left Port
R/WL
CEL
OEL
A14L-A0L
INTL
R/WR
CER
L
L
X
7FFF
X
X
X
X
X
X
X
X
X
L
X
X
X
X
L(3)
L
L
X
L
L
7FFE
H(2)
X
X
NOTES:
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. Refer to Chip Enable Truth Table.
Right Port
OER
A14R-A0R
X
X
L
7FFF
X
7FFE
X
X
INTR
Function
L(2) Set Right INTR Flag
H(3) Reset Right INTR Flag
X Set Left INTL Flag
X Reset Left INTL Flag
3199 tbl 16
61.452
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