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SIC402A

10 A microBUCK® SiC402A/B Integrated Buck Regulator with Programmable LDO

Vishay Semiconductors 

www.vishay.com

FB comparator

FB

VREP

-

+

Gate

drives VIN

DH

Q1

VLX L

VOUT

VIN

One-shot

DL

timer

Rton On-time = K x Rton x (VOUT/VIN)

ESR

Q2

COUT

+

VOUT

FB

Fig. 24 - On-Time Generation

This method automatically produces an on-time that is

proportional to VOUT and inversely proportional to VIN. Under

steady-state conditions, the switching frequency can be

determined from the on-time by the following equation.

fSW

=

VOUT

tON x VIN

The SiC402A/B uses an external resistor to set the on-time

which indirectly sets the frequency. The on-time can be

programmed to provide an operating frequency up to 1 MHz

using a resistor between the tON pin and ground. The

resistor value is selected by the following equation.

Rton =

k

25 pF x fsw

The constant, k, equals 1, when VDD is greater than 3.6 V.

If VDD is less than 3.6 V and VIN is greater than

(VDD - 1.75) x 10, k is shown by the following equation.

k = (VDD - 1.75) x 10

VIN

The maximum RtON value allowed is shown by the following

equation.

Rton_MAX. =

VIN_MIN.

15 µA

VOUT Voltage Selection

The switcher output voltage is regulated by comparing VOUT

as seen through a resistor divider at the FB pin to the internal

600 mV reference voltage, see figure 25.

VOUT

R1

R2

to FB pin

Fig. 25 - Output Voltage Selection

Note that this control method regulates the valley of the

output ripple voltage, not the DC value. The DC output

voltage VOUT is offset by the output ripple according to the

following equation.

VOUT = 0.6 x

1 + R1

R2

+

VRIPPLE

2

When a large capacitor is placed in parallel with R1 (CTOP) .

SiC402A, SiC402BCD

Vishay Siliconix

VOUT is shown by the following equation.

VOUT = 0.6 x

1+

R1

R2

+

VRIPPLE

2

x

1 + (R1ωCTOP)2

1+

R2

R2

x

+

R1

R1

ωCTOP

2

Enable and Power-Save Inputs

The EN/PSV input is used to enable or disable the switching

regulator. When EN/PSV is low (grounded), the switching

regulator is off and in its lowest power state. When off, the

output of the switching regulator soft-discharges the output

into a 500 k internal resistor via the VOUT pin. When

EN/PSV is allowed to float, the pin voltage will float to 33 %

of the voltage at VDD. The switching regulator turns on with

power-save disabled and all switching is in forced

continuous mode.

When EN/PSV is high (above 44 % of the voltage at VDD), the

switching regulator turns on with power-save enabled. The

SiC402A/B PSAVE operation reduces the switching

frequency according to the load for increased efficiency at

light load conditions.

Forced Continuous Mode Operation

The SiC402A/B operates the switcher in FCM (Forced

Continuous Mode) by floating the EN/PSV pin (see

figure 26). In this mode one of the power MOSFETs is always

on, with no intentional dead time other than to avoid

cross-conduction. This feature results in uniform frequency

across the full load range with the trade-off being poor

efficiency at light loads due to the high-frequency switching

of the MOSFETs. DH is gate signal to drive upper MOSFET.

DL is lower gate signal to drive lower MOSFET.

FB ripple

voltage (VFB)

Inductor

current

FB threshold

DC load current

On-time

(tON)

DH on-time is triggered when

VFB reaches the FB threshold

DH

DL

DL drives high when on-time is completed.

DL remains high until VFB falls to the FB threshold.

Fig. 26 - Forced Continuous Mode Operation

S14-2048-Rev. C, 13-Oct-14

11

Document Number: 63729

For technical questions, contact: powerictechsupport@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

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