HSP48410883 查看數據表（PDF） - Intersil

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HSP48410883

Histogrammer/Accumulating Buffer

Intersil 

HSP48410/883

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

Device Tested at: VCC = 5.0V ±10%, TA = -55oC to 125oC (Note 1)

PARAMETER

SYMBOL

NOTES

GROUP A

SUBGROUPS

TEMP (oC)

-33 (33MHz)

MIN MAX

-25 (25.6MHz)

MIN MAX

UNITS

Clock Period

t CP

9, 10, 11

-55 ≤ TA ≤ 125

30

-

39

-

ns

Clock Low

t CH

9, 10, 11

-55 ≤ TA ≤ 125

12

-

15

-

ns

Clock High

t CL

9, 10, 11

-55 ≤ TA ≤ 125

12

-

15

-

ns

DIN Setup

t DS

9, 10, 11

-55 ≤ TA ≤ 125

15

-

16

-

ns

DIN 0-23 Hold

t DH

9, 10, 11

-55 ≤ TA ≤ 125

1

-

1

-

ns

Clock to DIO 0-23 Valid

t DO

9, 10, 11

-55 ≤ TA ≤ 125

-

19

-

24

ns

FC Pulse Width

t FL

9, 10, 11

-55 ≤ TA ≤ 125

35

-

35

-

ns

FCT 0-2 Setup to LD

t FS

9, 10, 11

-55 ≤ TA ≤ 125

12

-

15

-

ns

FCT 0-2 Hold from LD

t FH

9, 10, 11

-55 ≤ TA ≤ 125

1

-

1

-

ns

START Setup to CLK

t SS

9, 10, 11

-55 ≤ TA ≤ 125

15

-

16

-

ns

START Hold from CLK

t SH

9, 10, 11

-55 ≤ TA ≤ 125

0

-

0

-

ns

PIN 0-9 Setup Time

t PS

9, 10, 11

-55 ≤ TA ≤ 125

15

-

16

-

ns

PIN 0-9 Hold Time

t PH

9, 10, 11

-55 ≤ TA ≤ 125

1

-

1

-

ns

LD Pulse Width

t LL

9, 10, 11

-55 ≤ TA ≤ 125

12

-

15

-

ns

LD Setup to START

t LS

Note 7

9, 10, 11

-55 ≤ TA ≤ 125

tCP

tCP

-

ns

WR Low

tWL

9, 10, 11

-55 ≤ TA ≤ 125

15

-

20

-

ns

WR High

t WH

9, 10, 11

-55 ≤ TA ≤ 125

15

-

20

-

ns

Address Setup

t AS

9, 10, 11

-55 ≤ TA ≤ 125

16

-

20

-

ns

Address Hold

t AH

9, 10, 11

-55 ≤ TA ≤ 125

2

-

2

-

ns

DIO Setup to WR

t WS

9, 10, 11

-55 ≤ TA ≤ 125

16

-

20

-

ns

DIO Hold from WR

t WH

9, 10, 11

-55 ≤ TA ≤ 125

2

-

2

-

ns

RD Low

t RL

9, 10, 11

-55 ≤ TA ≤ 125

43

-

55

-

ns

RD High

t RH

9, 10, 11

-55 ≤ TA ≤ 125

17

-

20

-

ns

RD Low to DIO Valid

t RD

9, 10, 11

-55 ≤ TA ≤ 125

-

43

-

55

ns

Output Enable Time

t OE

Note 8

9, 10, 11

-55 ≤ TA ≤ 125

-

19

-

24

ns

Read/Write Cycle Time

t CY

9, 10, 11

-55 ≤ TA ≤ 125

65

-

80

-

ns

NOTES:

6. AC Testing is performed as follows: Input levels (CLK) 0.0V and 4.0V; input levels (all other inputs) 0V and 3.0V. Timing reference levels (CLK)

= 2.0V, (all others) = 1.5V. Output load circuit with CL= 40pF. Output transition measured at VOH ≥ 1.5V and VOL ≥ 1.5V.

7. There must be at least one rising edge of CLK between the rising edge of LD and the falling edge of START.

8. Transition is measured at ±200 mV from steady state voltage with loading as specified in test load circuit with CL= 40pF.

5

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