V58C265164S-55 查看數據表（PDF） - Mosel Vitelic, Corp

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V58C265164S-55

64 Mbit DDR SDRAM 2.5 VOLT 4M X 16

Mosel Vitelic, Corp 

MOSEL VITELIC

V58C265164S

Burst Stop Command

The Burst Stop command is valid only during burst read cycles and is initiated by having RAS and CAS

high with CS and WE low at the rising edge of the clock. When the Burst Stop command is issued during a

burst Read cycle, both the output data (DQ) and data strobe (DQS) go to a high impedance state after a delay

(LBST) equal to the CAS latency programmed into the device. If the Burst Stop command is issued during a

burst Write cycle, the command will be treated as a NOP command.

Read Terminated by Burst Stop Command Timing

T0

CK, CK

Command

CAS Latency = 2

DQS

DQ

CAS Latency = 2.5

DQS

DQ

CAS Latency = 3

DQS

DQ

T1

T2

Read

BST

LBST

LBST

LBST

(CAS Latency = 2, 2.5, 3; Burst Length = 4)

T3

T4

T5

T6

NOP

NOP

NOP

NOP

D0 D1

D0 D1

D0 D1

V58C265164S Rev. 1.7 August 2001

15

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