V58C265164SL-4 查看數據表（PDF） - Mosel Vitelic, Corp

零件编号

产品描述 (功能)

比赛名单

V58C265164SL-4

64 Mbit DDR SDRAM 2.5 VOLT 4M X 16

Mosel Vitelic, Corp 

MOSEL VITELIC

T0

CK, CK

V58C265164S

Burst Write Timing

(CAS Latency = Any; Burst Length = 4)

T1

T2

T3

T4

Command

DQS(nom)

DQ(nom)

DQS(min)

WRITE

NOP

tWPRES

tWPREH

tDQSS

tQDQSH

NOP

tQDQSS

tQDQSS

NOP

tWPST

tQDQSH

D0

D1

D2

D3

tWPREH(min)

tWPRES(min)

tDQSS(min)

DQ(min)

DQS(max)

tWPRES(max)

D0

D1

D2

D3

tWPREH(max)

DQ(max)

tDQSS(max)

D0

D1

D2

D3

Once the burst of write data is concluded and given that no subsequent burst write operations are initiated,

the data strobe signal (DQS) transitions from a logic low level back to Hi-Z. This is referred to as the data

strobe “write postamble”. This transition happens nominally one-half clock period after the last data of the

burst cycle is latched into the device.

V58C265164S Rev. 1.7 August 2001

17

Share Link: