V58C265164SL-55 查看數據表（PDF） - Mosel Vitelic, Corp

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V58C265164SL-55

64 Mbit DDR SDRAM 2.5 VOLT 4M X 16

Mosel Vitelic, Corp 

MOSEL VITELIC

V58C265164S

Output Data (DQ) and Data Strobe (DQS) Timing Relative to the Clock (CK)

During Read Cycles

(CAS Latency = 2.5; Burst Length = 4)

T0

T1

T2

T3

T4

CK, CK

Command

READ

NOP

DQS

DQ

NOP

NOP

NOP

tDQSCK(max)

tDQSCK(min)

tAC(min)

tAC(max)

D0

D1

D2

D3

The minimum time during which the output data (DQ) is valid is critical for the receiving device (i.e., a mem-

ory controller device). This also applies to the data strobe during the read cycle since it is tightly coupled to

the output data. The minimum data output valid time (tDV) and minimum data strobe valid time (tDQSV) are de-

rived from the minimum clock high/low time minus a margin for variation in data access and hold time due to

DLL jitter and power supply noise.

V58C265164S Rev. 1.7 August 2001

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