GS882Z18B-66 查看數據表（PDF） - Unspecified

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GS882Z18B-66

8Mb Pipelined and Flow Through Synchronous NBT SRAMs

Unspecified 

Preliminary.

GS882Z18/36B-11/100/80/66

Burst Cycles

Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from

read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address

generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when

driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write

the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into

Load mode.

Burst Order

The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been

accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is Low, a linear burst

sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables

below for details.

FLXDrive™

The ZQ pin allows selection between NBT RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive

strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.

Mode Pin Functions

Mode Name

Pin Name State

Function

Burst Order Control

LBO

L

H or NC

Linear Burst

Interleaved Burst

Output Register Control

FT

L

H or NC

Flow Through

Pipeline

Power Down Control

L or NC

ZZ

H

Active

Standby, IDD = ISB

ByteSafe Data Parity Control

DP

L

H or NC

Check for Odd Parity

Check for Even Parity

Parity Enable

PE

L or NC

H

Activate 9th I/Os (x18/36 Mode)

Deactivate 9th I/Os (x16/32 Mode)

FLXDrive Output Impedance Control

ZQ

L

H

High Drive (Low Impedance)

Low Drive (High Impedance)

Note:

There are pull-up devices on the LBO, ZQ, DP and FT pins and a pull down device on the PE and ZZ pins, so those input pins can be

unconnected and the chip will operate in the default states as specified in the above table.

Enable / Disable Parity I/O Pins

This SRAM allows the user to configure the device to operate in Parity I/O active (x18 or x36) or in Parity I/O inactive (x16 or

x32) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Tying PE high

deactivates the 9th I/O of each byte, although the bit in each byte of the memory array remains active to store and recall parity bits

generated and read into the ByteSafe parity circuits.

Rev: 1.15 6/2001

11/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

© 1998, Giga Semiconductor, Inc.

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