LF3320 查看數據表（PDF） - LOGIC Devices

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LF3320

Horizontal Digital Image Filter

LOGIC Devices 

DEVICES INCORPORATED

FIGURE 12. SYMMETRIC COEFFICIENT SET EXAMPLES

LF3320

Horizontal Digital Image Filter

87654321

Even-Tap, Even-Symmetric

Coefficient Set

7654321

Odd-Tap, Even-Symmetric

Coefficient Set

8765

4321

Even-Tap, Odd-Symmetric

Coefficient Set

FIGURE 13. I/D REGISTER DATA PATHS

A

B

ALU

A

B

ALU

A

B

ALU

Delay Stage N–1

Delay Stage N

A

B

ALU

A

B

ALU

A

B

ALU

COEF 7

COEF 6

COEF 7

2

COEF 6

COEF 7

2

COEF 6

EVEN-TAP MODE

ODD-TAP MODE

ODD-TAP INTERLEAVE MODE

The ALUs can perform two operations:

A+B and B–A. Bit 0 of Configuration

Register 0 determines the operation of

the ALUs in Filter A.

Bit 0 of Configuration Register 2 deter-

mines the operation of the ALUs in Filter

B. A+B is used with

even-

symmetric coefficient sets. B–A is used

with odd-symmetric coefficient sets.

Also, either the A or B operand may be

set to 0. Bits 1 and 2 of Configuration

Register 0 and Configuration Register 2

control the ALU inputs in

Filters A and B respectively. A+0 or B+0

are used with asymmetric coefficient

sets.

Interleave/Decimation Registers

The Interleave/Decimation Registers (I/D

Registers) feed the ALU inputs. They

allow the device to filter up to sixteen data

sets interleaved into the same data stream

without having to separate the data sets.

The I/D Registers should be set to a length

equal to the number of data sets inter-

leaved together.

For example, if two data sets are inter-

leaved together, the I/D Registers should

be set to a length of two. Bits 1 through 4 of

Configuration Register 1 and Configura-

tion Register 3 determine the length of the

I/D Registers in Filters A and B respec-

tively.

The I/D Registers also facilitate using

decimation to increase the number of filter

taps. Decimation by N is accomplished by

reading the filter’s output once every N

clock cycles. The device supports decima-

tion up to 16:1. With no decimation, the

maximum number of filter taps is sixteen.

When decimating by N, the number of

filter taps becomes 16N because there are

N–1 clock cycles when the filter’s output is

not being read. The extra clock cycles are

used to calculate more filter taps.

When decimating, the I/D Registers

should be set to a length equal to the

decimation factor. For example, when

performing a 4:1 decimation, the I/D

Registers should be set to a length of

four. When decimation is disabled or

when only one data set (non-interleaved

data) is fed into the device, the I/D

Registers should be set to a length of

one.

Video Imaging Products

2-10

08/16/2000–LDS.3320-N

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