TDA9332H/N2 查看數據表（PDF） - Philips Electronics
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TDA9332H/N2 Datasheet PDF : 56 Pages
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Philips Semiconductors
I2C-bus controlled TV display processors
Preliminary specification
TDA933xH series
Table 26 Multi-sync mode
VGA
0
1
MODE
horizontal frequency fixed by internal
reference
multi-sync function switched on
Table 27 Extended slow start mode
ESS
0
1
EXTENDED SLOW START MODE
not active
active
Table 28 Long blanking mode
LBM
0
1
BLANKING MODE
adapted to standard (50 or 60 Hz)
fixed in accordance with 50 Hz standard
Table 29 Vertical free-running frequency in TV mode
VFF
FREQUENCY
0
50 Hz (SVF = 0) or 100 Hz (SVF = 1)
1
60 Hz (SVF = 0) or 120 Hz (SVF = 1)
Table 30 De-interlace phase
DIP
PHASE
0
delay of 1st field (start of synchronized VD
pulse coincides with H-flyback) with 0.5 H
1
delay of 2nd field with 0.5 H
Table 31 Switch-off in vertical overscan
OSO
0
1
MODE
switch-off undefined
switch-off in vertical overscan
Table 32 Select vertical frequency
SVF
MODE
0
vertical frequency is 50 or 60 Hz
1
vertical frequency is 100 or 120 Hz
Table 33 Enable vertical guard (RGB blanking)
EVG
0
1
VERTICAL GUARD MODE
not active
active
Table 34 Interlace
DL
0
1
STATUS
interlace
de-interlace
Table 35 Soft clipping level
VOLTAGE DIFFERENCE
SC1 SC0 BETWEEN SOFT CLIPPING AND
PWL
0
0
0% above PWL
0
1
5% above PWL
1
0
10% above PWL
1
1
soft clipping off
Table 36 Clamp pulse timing
HDCL
MODE(1)
0
normal timing
1
HDTV timing
Note
1. See Chapter “Characteristics”; note 13.
Table 37 Start line blanking (15 steps; 2 line locked clock
period per step; 1 line period is 440 LLC pulses)
LBL3 LBL2 LBL1 LBL0
0
0
0
0
0
1
1
1
1
1
1
1
START LINE
BLANKING(1)
+14 LLC
normal
−16 LLC
Note
1. See Chapter “Characteristics”; note 13.
Output status bits
Table 38 Power-on reset
POR
0
1
MODE
normal
power-down
Table 39 Field frequency indication
FSI
FREQUENCY
0
50 or 100 Hz
1
60 or 120 Hz
2002 Jun 04
14
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