TDA7502 查看數據表（PDF） - STMicroelectronics
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TDA7502 Datasheet PDF : 25 Pages
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TDA7502
3
SAI interface
Figure 4. SAI timings
SDI0-3
VALID
SAI interface
LRCKR
SCKR
(RCKP=0)
tsckpl
tdt
VALID
tlrh
tlrs
tsdis
tsdih
tsckr
tsckph
D02AU1357
Table 11. Cycles
Timing
Description
tsckr
tdt
tlrs
tlrh
tsdid
tsdih
tsckph
tsckpl
Minimum Clock Cycle
SCKR active edge to data out valid
LRCK setup time
LRCK hold time
SDI setup time
SDI hold time
Minimum SCK high time
Minimum SCK low time
Value
4TDSP
10
5
5
15
15
0.35 tsckr
0.35 tsckr
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Note: TDSP = dsp master clock cycle time = 1/FDSP
Figure 5. SAI protocol when RLRS=0; RREL=0; RCKP=1; RDIR=0
LRCKR (#23)
SCKR (#24)
LEFT
RIGHT
SDI0,1,2 (#20, #21, #22)
LSB(n-1) MSB(word n) MSB-1 (n)
MSB-2 (n)
D02AU1358
11/25
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