RV5C386A-E2 查看數據表（PDF） - RICOH Co.,Ltd.

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RV5C386A-E2

I2C-Bus Real-Time Clock ICs with Voltage Monitoring Function

RICOH Co.,Ltd. 

RV5C386A

PRELIMINARY

14.8.4. Interrupt Process

(1) Periodic Interrupt

Set Periodic Interrupt *1)

Cycle Selection Bits

Generate Interrupt to CPU

*1) This step is intended to select the level mode as a

waveform mode for the periodic interrupt function.

*2) This step is intended to set the CTFG bit to 0 in the

Control Register 2 to cancel an interrupt to the

CPU.

CTFG=1?

No

Yes

Conduct

Periodic Interrupt

*2)

Control Register 2←

(X1X1X011)

Other Interrupt

Processes

(2) Alarm Interrupt

WALE or DALE←0 *1)

Set Alarm Min., Hr., and

Fay-of-week Registers

WALE or DALE←1 *2)

Generate Interrupt to CPU

*1) This step is intended to once disable the alarm

interrupt circuit by setting the WALE or DALE bits to 0

in anticipation of the coincidental occurrence of a

match between current time and preset alarm time in

the process of setting the alarm interrupt function.

*2) This step is intended to enable the alarm interrupt

function after completion of all alarm interrupt

settings.

*3) This step is intended to once cancel the alarm

interrupt function by writing the settings of "X,1,X,

1,X,1,0,1" and "X,1,X,1,X,1,1,0" to the Alarm_W

Registers and the Alarm_D Registers, respectively.

WAFG or DAFG=1?

Yes

Conduct Alarm Interrupt

No Other Interrupt

Processes

*3)

Control Register 2 ←

(X1X1X101)

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