MB86615 查看數據表（PDF） - Fujitsu

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产品描述 (功能)

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MB86615

IEEE 1394 Bus Controller (for DVC)

Fujitsu 

MB86615

(4) Negating ILWRE during Transmission (with a bus reset detected or the FIFO buffer full)

Parameter

ICLK rise to ILWRE rise time

ILWRE rise to IV rise time

ICLK rise to ILWRE fall time

Symbol

tHWRL

tREMIV

tHWRH

Min.

—

tICLK

—

Value

Max.

40

2 tICLK – 40

40

Unit

ns

ns

ns

ICLK

IDIR

ILWRE

IV

ID7 to ID0

valid

tHWRL

tREMIV

valid

valid

tHWRH

ignore

Note: The ILWRE signal is negated to stop writing data to be transmitted in either of the following cases in the

transmission mode

(1) When the ISO transmission/reception FIFO buffer becomes full (The ILWRE signal is negated in

synchronization with the last ICLK signal generated before the FIFO buffer becomes full. Note, however,

that this condition does not negate the ILWRE signal if the point-rcc bit (bit 7) in the ISO-FIFO control

register (address 0Eh) has been set to “1.”

(2) When a bus reset is detected (The ILWRE signal is negated in synchronization with the last ICLK signal

generated before the FIFO buffer loads one packet of data after detection of the bus reset.)

The ILWRE signal is asserted back when transmission of one packet of data to the 1394 bus is completed.

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