V58C265804SLT7 查看數據表（PDF） - Mosel Vitelic, Corp

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V58C265804SLT7

HIGH PERFORMANCE 2.5 VOLT 8M X 8 DDR SDRAM 4 BANKS X 2Mbit X 8

Mosel Vitelic, Corp 

MOSEL VITELIC

V58C265804S

Precharge Timing During Read Operation

For the earliest possible Precharge command without interrupting a Read burst, the Precharge command

may be issued on the rising clock edge which is CAS latency (CL) clock cycles before the end of the Read

burst. A new Bank Activate (BA) command may be issued to the same bank after the RAS precharge time

(tRP). A Precharge command can not be issued until tRAS(min) is satisfied.

Read with Precharge Timing as a Function of CAS Latency

(CAS Latency = 2, 2.5, 3; Burst Length = 4)

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

tRAS(min)

tRP(min)

CK, CK

Command BA NOP

NOP

Read

NOP

PreA

NOP

BA

NOP

NOP

DQS

DQ

DQS

DQ

DQS

DQ

D0 D1 D2 D3

CAS Latency=2

D0 D1 D2 D3

CAS Latency=2.5

D0 D1 D2 D3

CAS Latency=3

V58C265804S Rev. 1.3 January 2000

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