V58C265804ST6 查看數據表（PDF） - Mosel Vitelic, Corp
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V58C265804ST6 Datasheet PDF : 44 Pages
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MOSEL VITELIC
V58C265804S
Data Mask Function
The DDR SDRAM has a Data Mask function that is used in conjunction with the Write cycle, but not the
Read cycle. When the Data Mask is activated (DM high) during a Write operation, the Write is blocked (Mask
to Data Latency = 0).
When issued, the Data Mask must be referenced to both the rising and falling edges of Data Strobe.
Data Mask Timing
T0
CK, CK
Command
DQS
DQ
(CAS Latency = Any; Burst Length = 8)
T1
T2
T3
T4
T5
T6
T7
T8
T9
Write
NOP
tDMDQSS
NOP
NOP
NOP
NOP
NOP
tDMDQSS
NOP
tDMDQSH
D0 D1 D2 D3 D4 D5 D6 D7
tDMDQSH
DM
Burst Interruption
Read Interrupted by a Read
A Burst Read can be interrupted before completion of the burst by issuing a new Read command to any
bank. When the previous burst is interrupted, the remaining addresses are overridden with a full burst length
starting with the new address. The data from the first Read command continues to appear on the outputs until
the CAS latency from the interrupting Read command is satisfied. At this point, the data from the interrupting
Read command appears on the bus. Read commands can be issued on each rising edge of the system clock.
It is illegal to interrupt a Read with autoprecharge command with a Read command.
Read Interrupted by a Read Command Timing
(CAS Latency = 2; Burst Length = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CK, CK
Command
ReadA ReadB
NOP
NOP
NOP
NOP
NOP
NOP
DQS
DQ
DA0 DA1 DB0 DB1 DB2 DB3
V58C265804S Rev. 1.3 January 2000
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