V58C265404S-6 查看數據表（PDF） - Mosel Vitelic, Corp

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V58C265404S-6

HIGH PERFORMANCE 2.5 VOLT 16M X 4 DDR SDRAM 4 BANKS X 4Mbit X 4

Mosel Vitelic, Corp 

MOSEL VITELIC

V58C265404S

Precharge Timing During Write Operation

Precharge timing for Write operations in DRAMs requires enough time to satisfy the write recovery require-

ment. This is the time required by a DRAM sense amp to fully store the voltage level. For DDR SDRAMs, a

timing parameter (tWR) is used to indicate the required amount of time between the last valid write operation

and a Precharge command to the same bank.

The “write recovery” operation begins on the rising clock edge after the last DQS edge that is used to strobe

in the last valid write data. “Write recovery” is complete on the next rising clock edge that is used to strobe in

the Precharge command.

For the earliest possible Precharge command following a Write burst without interrupting the burst, the

minimum time for “write recovery” is 1.25 clock cycles. Maximum “write recovery” time is 1.75 clock cycles.

Write with Precharge Timing

(CAS Latency = Any; Burst Length = 4)

T0

T1

CK, CK

Command

BA NOP

DQS

DQ

DQS

DQ

T2

T3

T4

T5

T6

T7

tRAS(min)

NOP

Write

NOP

NOP

NOP

PreA

tWR(min)

D0 D1 D2 D3

tWR(max)

D0 D1 D2 D3

T8

T9

tRP(min)

NOP

BA

V58C265404S Rev. 1.4 January 2000

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