MAX2079CXET 查看數據表（PDF） - Maxim Integrated

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MAX2079CXET

Low-Power, High-Performance, Fully Integrated Octal Ultrasound Receiver (Octal LNA, VGA, AAF, ADC, and CWD Beamformer)

Maxim Integrated 

MAX2079

Low-Power, High-Performance, Fully Integrated

Octal Ultrasound Receiver (Octal LNA, VGA,

AAF, ADC, and CWD Beamformer)

ELECTRICAL CHARACTERISTICS—CLOCK AND TIMING (continued)

(VREF = 2.5V, VCC3 = 3.13V to 3.47V, VCC5 = 4.5V to 5.25V, VAVDD = VOVDD = 1.7V to 1.9V, TA = 0NC to +70NC, VGND = 0V, SHDN = 0,

CWD = 0, LOON = 0. fRF = 5MHz, 50mVP-P, ADC fCLK = 50Msps, digital HPF set to 60/64, two poles, 15/16 digital gain, VGC+ -

VGC- = -3V (minimum gain), high LNA gain. Typical values are at VREF = 2.5V, VCC3 = 3.3V, VCC5 = 4.75V, VAVDD = VOVDD = 1.8V,

VGC+ - VGC- = 0V, TA = +25NC, unless otherwise noted.) (Note 3)

Note 3: Minimum and maximum limits at TA = +25NC and +70NC are guaranteed by production test. Specifications for

TA < +25NC are guaranteed by design and/or characterization.

Note 4: Noise performance of the device is dependent on the noise contribution from VREF. Use a low-noise supply for VREF.

Note 5: This response time does not include the CW output highpass filter. When switching to VGA mode, the CW outputs stop

drawing current and the output voltage goes to the rail. If a highpass filter is used, the recovery time can be excessive

and a switching network is recommended.

Note 6: Specifications are guaranteed by design and characterization.

Note 7: See Figure 22 in the Ultrasound-Specific IMD3 Specification section.

Note 8: The LVDS CWD LO inputs are DC-coupled. See the CWD Beamformer Programming and Clocking section for details of

LO startup synchronization.

Note 9: An external 100I resistor terminates the LVDS differential signal path (LO+, LO-).

Note 10: The reference input noise is given for 8 channels, knowing that the reference-noise contributions are correlated in all 8

channels. If more channels are used, the reference noise must be reduced to get the best noise performance.

Note 11: Total on-chip power dissipation is calculated as PDISS = VCC5 x ICC5 + VCC3 x ICC3 + VAVDD x IAVDD + VOVDD x IOVDD

+ VREF x IREF + [11V - (I11V/4) x 120] x I11V. Additional power is dissipated through the off-chip 120I load resistors.

Note 12: Mixer output-voltage compliance is the range of acceptable voltages allowed on the CW mixer outputs.

Note 13: Transconductance is defined as the differential output current at baseband for each individual (I or Q) mixer output,

divided by the single-ended RF input voltage directly on a single LNA input pin (INj). This can be calculated as gmI =

(ICI+ - ICI-)/VINj and gmQ = (ICQ+ - ICQ-)/VINj; or equivalently as gmI = (VCI+ - VCI-)/(RL x VINj) and gmQ = (ICQ+ - ICQ-)/

(RL x VINj) (where j = 1, 2, …8 is a specific channel number, INj is a single LNA input pin, and RL is the load resistance

on each individual mixer output pin).

LO+

LVDS

LO

LO-

LOON

CWD LOON (LO On/Off) Timing Detail

tSU

Maxim Integrated

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