MAX2079CXET 查看數據表（PDF） - Maxim Integrated
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MAX2079CXET Datasheet PDF : 49 Pages
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MAX2079
Low-Power, High-Performance, Fully Integrated
Octal Ultrasound Receiver (Octal LNA, VGA,
AAF, ADC, and CWD Beamformer)
ELECTRICAL CHARACTERISTICS—CLOCK AND TIMING (continued)
(VREF = 2.5V, VCC3 = 3.13V to 3.47V, VCC5 = 4.5V to 5.25V, VAVDD = VOVDD = 1.7V to 1.9V, TA = 0NC to +70NC, VGND = 0V, SHDN = 0,
CWD = 0, LOON = 0. fRF = 5MHz, 50mVP-P, ADC fCLK = 50Msps, digital HPF set to 60/64, two poles, 15/16 digital gain, VGC+ -
VGC- = -3V (minimum gain), high LNA gain. Typical values are at VREF = 2.5V, VCC3 = 3.3V, VCC5 = 4.75V, VAVDD = VOVDD = 1.8V,
VGC+ - VGC- = 0V, TA = +25NC, unless otherwise noted.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
SERIAL-PORT INTERFACE TIMING
SCLK Period
SCLK-to-CS Setup Time
SCLK-to-CS Hold Time
SDIO-to-SCLK Setup Time
SDIO-to-SCLK Hold Time
tSCLK
tCSS
tCSH
tSDS
tSDH
Serial-data write
Serial-data write
SCLK-to-SDIO Output Data
Delay
tSDD Serial-data read
MIN
TYP
MAX UNITS
50
ns
10
ns
10
ns
10
ns
0
ns
10
ns
LVDS DIGITAL OUTPUT TIMING CHARACTERISTICS
Data Valid to CLKOUT_ Rise/Fall
tOD
(tSAMPLE/ (tSAMPLE/ (tSAMPLE/
24) - 0.10 24) + 0.05 24) + 0.20
ns
CLKOUT_ Output-Width High
tCH
tSAMPLE/
12
ns
CLKOUT_ Output-Width Low
tCL
tSAMPLE/
12
ns
FRAME_ Rise to CLKOUT_ Rise
tDF
(tSAMPLE/ (tSAMPLE/ (tSAMPLE/
24) - 0.10 24) + 0.05 24) + 0.20
ns
Sample CLKIN_ Rise to
FRAME_ Rise
tSF
(tSAMPLE/ (tSAMPLE/ (tSAMPLE/
2) + 1.6 24) + 2.3 2) + 3.3
ns
CWD LO TIMING
LOON Setup Time
tSU
Setup time from LOON high to LVDS LO
clock low-to-high transition
5
ns
Maxim Integrated
9
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