ST16C554CJ-0A-EVB 查看數據表（PDF） - Unspecified

零件编号

产品描述 (功能)

比赛名单

ST16C554CJ-0A-EVB

2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO

Unspecified 

ST16C554/554D/68C554

SYMBOL DESCRIPTION

Symbol

-RESET

RESET

-R/W

-RXRDY

-TXRDY

VCC

VCC

Pin

Signal

68

64 type

Pin Description

37

18

38

39

13

47,64

27

I Reset. - In the 16 mode a logic 1 on this pin will reset the

internal registers and all the outputs. The UART transmitter

output and the receiver input will be disabled during reset

time. (See ST16C554D External Reset Conditions for ini-

tialization details.) When 16/-68 is a logic 0 (68 mode), this

pin functions similarly but, as an inverted reset interface

signal, -RESET.

-

I Read/Write Strobe (active low) - This function is associated

with the 68 mode only. This pin provides the combined

functions for Read or Write strobes. A logic 1 to 0 transition

transfers the contents of the CPU data bus (D0-D7) to the

register selected by -CS and A0-A4. Similarly a logic 0 to 1

transition places the contents of a 554D register selected by

-CS and A0-A4 on the data bus, D0-D7, for transfer to an

external CPU.

-

O Receive Ready (active low) - This function is associated

with 68 pin packages only. -RXRDY contains the wire “OR-

ed” status of all four receive channel FIFOs, RXRDY A-D.

A logic 0 indicates receive data ready status, i.e. the RHR

is full or the FIFO has one or more RX characters available

for unloading. This pin goes to a logic 1 when the FIFO/RHR

is full or when there are no more characters available in

either the FIFO or RHR. For 64/68 pin packages, individual

channel RX status is read by examining individual internal

registers via -CS and A0-A4 pin functions.

-

O Transmit Ready (active low) - This function is associated

with 68 pin package only. -TXRDY contains the wire “OR-

ed” status of all four transmit channel FIFOs, TXRDY A-D.

A logic 0 indicates a buffer ready status, i.e., at least one

location is empty and available in one of the TX channels (A-

D). This pin goes to a logic 1 when all four channels have no

more empty locations in the TX FIFO or THR.

4,21

35,52 I Power supply inputs.

Rev. 3.10

8

Share Link: