CY7C1460AV25 查看數據表（PDF） - Cypress Semiconductor

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CY7C1460AV25

36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL™ Architecture

Cypress Semiconductor 

CY7C1460AV25

CY7C1462AV25

CY7C1464AV25

Pin Configurations (continued)

209-ball FBGA (14 x 22 x 1.76 mm) Pinout

CY7C1464AV25 (512K x 72)

1

2

3

4

5

6

7

8

9

10

11

A

DQg

DQg

A

CE2

A

ADV/LD A

CE3

A

DQb

DQb

B

DQg DQg

BWSc BWSg

NC WE

A

BWSb BWSf DQb DQb

C

DQg DQg

BWSh BWSd NC/576M CE1

NC

BWSe BWSa DQb

DQb

D

DQg DQg

VSS

NC

NC/1G OE

NC

NC

VSS

DQb

DQb

E

DQPg DQPc VDDQ VDDQ VDD

VDD

VDD

VDDQ VDDQ DQPf DQPb

F

DQc

DQc

VSS

VSS

VSS

NC

VSS

VSS

VSS

DQf

DQf

G

DQc

DQc

VDDQ VDDQ

VDD

NC

VDD

VDDQ

VDDQ

DQf

DQf

H

DQc

DQc

VSS

VSS

VSS

NC

VSS

VSS

VSS

DQf

DQf

J

DQc

DQc

VDDQ VDDQ

VDD

NC

VDD

VDDQ VDDQ

DQf

DQf

K

NC

NC

CLK

NC

VSS

CEN

VSS

NC

NC

NC

NC

L

DQh

DQh VDDQ

VDDQ

VDD

NC

VDD

VDDQ

VDDQ

DQa

DQa

M

DQh

DQh VSS

VSS

VSS

NC

VSS

VSS

VSS

DQa DQa

N

DQh

DQh VDDQ

VDDQ

VDD

NC

VDD

VDDQ

VDDQ

DQa

DQa

P

DQh DQh VSS

VSS

VSS

ZZ

VSS

VSS

VSS

DQa DQa

R

DQPd DQPh VDDQ VDDQ

VDD

VDD

VDD

VDDQ

VDDQ DQPa DQPe

T

DQd DQd VSS

NC

NC

MODE NC

NC

VSS

DQe DQe

U

DQd DQd NC/144M A

NC/72M A

A

A

NC/288M DQe

DQe

V

DQd DQd

A

A

A

A1

A

A

A

DQe DQe

W

DQd DQd TMS

TDI

A

A0

A

TDO

TCK

DQe DQe

Pin Definitions

Pin Name

A0

A1

A

BWa

BWb

BWc

BWd

BWe

BWf

BWg

BWh

WE

ADV/LD

CLK

I/O Type

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Input-

Clock

Pin Description

Address Inputs used to select one of the address locations. Sampled at the rising edge of

the CLK.

Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.

Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb,

BWc controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQPe, BWf

controls DQf and DQPf, BWg controls DQg and DQPg, BWh controls DQh and DQPh.

Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This

signal must be asserted LOW to initiate a write sequence.

Advance/Load Input used to advance the on-chip address counter or load a new address.

When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a

new address can be loaded into the device for an access. After being deselected, ADV/LD should

be driven LOW in order to load a new address.

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.

CLK is only recognized if CEN is active LOW.

Document #: 38-05354 Rev. *D

Page 5 of 27

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