MTD800 查看數據表（PDF） - Myson Century Inc

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MTD800

Integrated Fast Ethernet Controller

Myson Century Inc 

MYSON

TECHNOLOGY

MTD 800

(Preliminary)

Name

Field

Reser ved

Bit 3

Memor y Wr ite and Bit 4

Invalidate

Reser ved

Bit 5

Par ity Er ror

Bit 6

Response

Reser ved

Bit

7~15

Descr iption

This field is har dwir ed to 0.

The value is 0 after har dware r eset.

This bit is readable and writable. A value of 1 allows the device to

generate Memory Write and Invalidate command, else a value of 0

prohibits generating the command.

This field is har dwir ed to 0.

The value is 0 after har dware r eset.

This bit is readable and writable. A value of 1 allows the device to

take a normal action, like asserting PERR_, when parity error is

detected. Otherwise it ignores the detection and continues to oper-

ate.

This field is har dwir ed to 0.

4.1.3 Status Register - 06H (CFSR)

The status register is located at the configuration address of 06H.

Table 4.4 Bit Definition of the Status Register

Name

Reser ved

Power Manage-

ment Capability

Reser ved

Fast Back-to-Back

Capable

Field

Bit 0~3

Bit 4

Bit 5~6

Bit 7

Descr iption

This field is har dwir ed to 0.

The value of this field is loaded from EEPROM.

A value of 1 indicates that Power Management function is imple-

mented in the device. And it meets the requirement of PCI Bus

Power Management Interface Specification.

This field is har dwir ed to 0.

This field is har dwir ed to 1.

A value of 1 indicates the device is able to accept the operation of

Fast Back-to-Back which is activated by different masters.

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MTD800 Revision 0.0 07/20/1999

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