HEF4043B-Q100 查看數據表（PDF） - NXP Semiconductors.

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HEF4043B-Q100

Quad R/S latch with 3-state outputs

NXP Semiconductors. 

NXP Semiconductors

HEF4043B-Q100

Quad R/S latch with 3-state outputs

a. Input waveform

VI

negative

pulse

0V

VI

positive

pulse

0V

90 %

10 %

VM

10 %

tf

tr

90 %

VM

tW

90 %

VM

10 %

tr

tf

90 %

VM

10 %

tW

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VI

G

VDD

DUT

VEXT

VO

RL

RT

CL

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b. Test circuit

Fig 6.

Test and measurement data is given in Table 10.

Definitions test circuit:

DUT = Device Under Test.

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

CL = Load capacitance including jig and probe capacitance.

Test circuit for measuring switching times

Table 10. Test data

Supply voltage

5 V to 15 V

Input

VI

VDD

tr, tf

 20 ns

Load

CL

50 pF

RL

1 k

VEXT

tPLH, tPHL

open

tPLZ, tPZL

VDD

tPHZ, tPZH

GND

HEF4043B_Q100

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 15 July 2013

© NXP B.V. 2013. All rights reserved.

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