AD7452BRTZ-REEL7 查看數據表（PDF） - Analog Devices
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AD7452BRTZ-REEL7 Datasheet PDF : 24 Pages
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AD7452
Data Sheet
Parameter
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time3
Throughput Rate
POWER REQUIREMENTS
VDD
IDD9, 10
Normal Mode (Static)
Normal Mode (Operational)
Full Power-Down Mode
Power Dissipation
Normal Mode (Operational)
Full Power-Down
Test Conditions/Comments
1.6 µs with a 10 MHz SCLK
Sine wave input
Step input
Range: 3 V + 20%/–10%;
5 V ± 5%
SCLK on or off
VDD = 4.75 V to 5.25 V
VDD = 2.7 V to 3.6 V
SCLK on or off
VDD = 5 V, 1.55 mW typ for 100 kSPS9
VDD = 3 V, 0.64 mW typ for 100 kSPS9
VDD = 5 V, SCLK on or off
VDD = 3 V, SCLK on or off
B Version2
16
200
290
555
2.7/5.25
0.5
1.5
1.2
1
7.25
3.3
5
3
Unit
SCLK cycles
ns max
ns max
kSPS max
V min/V max
mA typ
mA max
mA max
µA max
mW max
mW max
µW max
µW max
1 Common-mode voltage. The input signal can be centered on a dc common-mode voltage in the range specified in Figure 23 and Figure 24.
2 Temperature ranges as follows: B Version: –40°C to +85°C.
3 See Terminology section.
4 Analog inputs with slew rates exceeding 27 V/µs (full-scale input sine wave > 3.5 MHz) within the acquisition time may cause an incorrect result to be returned by the
converter.
5 Because the input spans of VIN+ and VIN– are both VREF and are 180° out of phase, the differential voltage is 2 × VREF.
6 The AD7452 is functional with a reference input from 100 mV; for VDD = 5 V, the reference can range up to 3.5 V.
7 The AD7452 is functional with a reference input from 100 mV; for VDD = 3 V, the reference can range up to 2.2 V.
8 Guaranteed by characterization.
9 See Power VS. Throughput Rate section.
10 Measured with a midscale dc input.
Rev. C | Page 4 of 24
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