AD9204(RevA) 查看數據表（PDF） - Analog Devices
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AD9204
(Rev.:RevA)
(Rev.:RevA)
Analog Devices
AD9204 Datasheet PDF : 36 Pages
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Data Sheet
AD9204
SWITCHING SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,
DCS disabled, unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate1
CLK Period—Divide-by-1 Mode (tCLK)
CLK Pulse Width High (tCH)
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
DATA OUTPUT PARAMETERS
Data Propagation Delay (tPD)
DCO Propagation Delay (tDCO)
DCO to Data Skew (tSKEW)
Pipeline Delay (Latency)
Wake-Up Time2
Standby
OUT-OF-RANGE RECOVERY TIME
AD9204-20/AD9204-40
Temp Min Typ
Max
AD9204-65
AD9204-80
Min Typ Max Min Typ Max Unit
Full
625
625
625 MHz
Full 3
20/40 3
65 3
80 MSPS
Full 50/25
15.38
12.5
ns
25.0/12.5
7.69
6.25
ns
Full
1.0
1.0
1.0
ns
Full
0.1
0.1
0.1
ps rms
Full
3
Full
3
Full
0.1
Full
9
Full
350
Full
600/400
Full
2
3
3
ns
3
3
ns
0.1
0.1
ns
9
9
Cycles
350
350
μs
300
260
ns
2
2
Cycles
1 Conversion rate is the clock rate after the CLK divider.
2 Wake-up time is dependent on the value of the decoupling capacitors.
N–1
tA
N
VIN
N+3
N+4
N+5
N+1
N+2
CLK+
CLK–
DCOA/DCOB
tCH
tCLK
tDCO
tSKEW
CH A/CH B DATA
N–9
N–8
N–7
N–6
N–5
tPD
Figure 2. CMOS Output Data Timing
N–1
tA
N
VIN
N+3
N+4
N+5
N+1
N+2
CLK+
tCH
tCLK
CLK–
DCOA/DCOB
tDCO
CH A/CH B DATA
AS APPEARS ON
CHA OUTPUT PINS
tSKEW
CH A CH B
N–9 N–9
tPD
CH A
N–8
CH B
N–8
CH A
N–7
CH B
N–7
CH A
N–6
CH B
N–6
Figure 3. CMOS Interleaved Output Timing, Output as Appears on the Channel A Output Pins
CH A
N–5
Rev. A | Page 7 of 36
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