AD9731 查看數據表（PDF） - Analog Devices

零件编号

产品描述 (功能)

比赛名单

AD9731

10-Bit, 170 MSPS D/A Converter

Analog Devices 

AD9731

SPECIFICATIONS

Parameter

Temp

Test

Level

Min

Typ

Max

Unit

SFDR PERFORMANCE (Narrowband)13

2 MHz; 2 MHz Span

25∞C

V

25 MHz, 2 MHz Span

25∞C

V

10 MHz, 5 MHz Span (Clock = 170 MHz)

25∞C

V

INTERMODULATION DISTORTION14

F1 = 800 kHz, F2 = 900 kHz

25∞C

V

POWER SUPPLY15

Digital –V Supply Current

Analog –V Supply Current

Digital +V Supply Current

Power Dissipation

PSRR

25∞C

I

Full

VI

25∞C

I

Full

VI

25∞C

I

Full

VI

25∞C

V

Full

V

25∞C

V

79

61

73

58

27

37

27

42

45

53

45

66

13

20

15

22

439

449

100

dB

dB

dB

dB

mA

mA

mA

mA

mA

mA

mW

mW

mA/V

NOTES

1Measured as an error in ratio of full-scale current to current through R SET (640 mA nominal); ratio is nominally 32. DAC load is virtual ground.

2Internal reference voltage is tested under load conditions specified in Internal Reference Output current specification.

3Internal reference output current defines load conditions applied during Internal Reference Voltage test.

4Full-scale current variations among devices are higher when driving REFERENCE IN directly.

5Frequency at which a 3 dB change in output of DAC is observed; RL = 50 W; 100 mV modulation at midscale.

6Based on IFS = 32 (CONTROL AMP IN/RSET) when using internal control amplifier. DAC load is virtual ground.

7Measured as voltage settling at midscale transition to ± 0.5 LSB, RL = 50 W.

8Measured from 50% point of rising edge of CLOCK signal to 1/2 LSB change in output signal.

9Peak glitch impulse is measured as the largest area under a single positive or negative transient.

10Measured with RL = 50 W and DAC operating in latched mode.

11Data must remain stable for specified time prior to rising edge of CLOCK.

12Data must remain stable for specified time after rising edge of CLOCK.

13SFDR is defined as the difference in signal energy between the full-scale fundamental signal and worst-case spurious frequencies in the output spectrum window.

The frequency span is dc-to-Nyquist unless otherwise noted.

14Intermodulation distortion is the measure of the sum and difference products produced when a two-tone input is driven into the DAC. The distortion products

created will manifest themselves at (2F2–F1) and (2F1–F2) of the two tones.

15Supply voltages should remain stable within ± 5% for nominal operation.

Specifications subject to change without notice.

p w MIN

p w MAX

CLOCK

DATA

tS

CODE 1

DATA

tH

CODE 2

DATA

CODE 3

DATA

CODE 4

DATA

CODE 2

ANALOG OUTPUT

CODE 1

CODE 4

CODE 3

REV. B

DETAIL OF SETTLING TIME

CLOCK

t PD

ANALOG OUTPUT

SPECIFIED

ERROR BAND

t ST

Figure 1. Timing Diagrams

–3–

GLITCH AREA =

1/2 HEIGHT ؋ WIDTH

H

W

Share Link: