UPD16681 查看數據表（PDF） - NEC => Renesas Technology

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UPD16681

LCD CONTROLLER/DRIVER FOR DOT MATRIX DISPLAY OF JIS LEVEL 1 AND JIS LEVEL 2 KANJI SETS

NEC => Renesas Technology 

µPD16681

3.2 Logic System Pins

Pin Symbol

Pin Name

WS

Select word length

Pad No.

76

DACHA

Select D/A converter 61

STB

Strobe

77

E/SCK

Enable/shift clock

78

D0/DATA

Data bus/data

68

D1-D7

Data bus

69-75

TESTOUT

Test output

80

/RESET

Reset

79

AMPCHA

VEXT

SEGINV

COMINV

• OSCIN

Op amp switch for

62

LCD driver’s power

supply level

Reference power

60

supply switch

Segment direction

63

switch

Common scan

64

direction switch

Oscillator pins

65

OSCOUT

66

OSCBRI

External clock for

67

blink function

I/O

Description

I Use this pin to select the word length. An 8-bit parallel interface is used

for high level and a serial interface is used for low level. This setting

cannot be changed after the power has been switched on.

I Use this pin to select whether or not to use the D/A converter for

regulating the LCD driver voltage. Select high level to use the D/A

converter or low level to not use it.

I This is used for the device’s select signal and strobe signal for

communication. Communication is initialized at the rising edge or falling

edge of STB.

Command data receive standby status occurs at the falling edge of STB.

Communication is enabled when STB is low.

Also, enabled status or the shift clock is ignored when STB is high.

I This is an input enable pin for data when the parallel interface is used.

During the read-in operation, data is captured in the interface buffer at

the signal’s rising edge. During a read-out operation, data is read-out

from the interface buffer at the signal’s falling edge.

When using a serial interface, this pin is used for the data shift clock.

During the read-in operation, data is captured in the shift register at the

signal’s rising edge. During a read-out operation, data is read from the

shift register at the signal’s falling edge.

I/O This pin is used for data bus bit D0 when using the parallel interface.

When using the serial interface, it is an I/O pin (tri-state) for commands

and display data.

I/O These pins are used for data bus bits D1 to D7 when using the parallel

interface.

It should be fixed high or low when using the serial interface.

O This is a test output pin. Leave this pin open when using the device.

I This pin is used for internal resets at low-level.

I This pin is used to control the op amp that works with the LCD driver’s

power supply level. High-power mode is set when at low level and

normal mode is set when at high level.

I This pin is used to select the reference power supply circuit’s supply

mode. High level sets external mode and low level sets internal mode.

I This pin is used to control the segment output direction. Low level sets

forward direction and high level sets reverse direction.

I This pin is used to switch the common scan direction. Low level sets

forward direction and high level sets reverse direction.

I These pins are connected to a 100-kΩ resistance. When using an

O external oscillator, input to OSCIN and leave OSCOUT unconnected.

I This is an input pin for the 2-Hz external clock. Internally, it is divided by

half to generate a 1-Hz signal that is used as the synchronization signal

for the blink function.

6

Data Sheet S13104EJ5V0DS00

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