DS80C390-FCR 查看數據表（PDF） - Maxim Integrated
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DS80C390-FCR Datasheet PDF : 52 Pages
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DS80C390 Dual CAN High-Speed Microprocessor
AC ELECTRICAL CHARACTERISTICS—(MULTIPLEXED ADDRESS/DATA BUS)
(Note 10, Note 11)
PARAMETER
Oscillator Frequency
ALE Pulse Width
Port 0 Instruction Address or CE0--4
Valid to ALE Low
SYMBOL
1 / tCLCL
CONDITIONS
External oscillator
External crystal
40MHz
MIN MAX
0
40
1
40
tLHLL
tAVLL
VARIABLE CLOCK
MIN
MAX
0
40
1
40
0.375 tMCS
-5
0.125 tMCS - 5
UNITS
MHz
ns
ns
Address Hold After ALE Low
tLLAX1
0.125 tMCS - 5
ns
ALE Low to Valid Instruction In
ALE Low to PSEN Low
PSEN Pulse Width
PSEN Low to Valid Instruction In
Input Instruction Hold After PSEN
Input Instruction Float After PSEN
tLLIV
tLLPL
tPLPH
tPLIV
tPXIX
tPXIZ
0.625 tMCS - 20 ns
0.125 tMCS - 5
ns
0.5 tMCS - 8
ns
0.5 tMCS - 20
ns
0
0
ns
0.25 tMCS - 5
ns
Port 0 Address to Valid Instruction In
Port 2, 4 Address to Valid Instruction
In
PSEN Low to Address Float
tAVIV1
tAVIV2
tPLAZ
0.75 tMCS - 22 ns
0.875 tMCS - 30 ns
0
0
ns
Note 11:
All parameters apply to both commercial and industrial temperature operation unless otherwise noted. The value tMCS is a function
of the machine cycle clock in terms of the processor’s input clock frequency. These relationships are described in the Stretch Value
Timing table. All signals characterized with load capacitance of 80pF except Port 0, ALE, PSEN, RD, and WR with 100pF.
Interfacing to memory devices with float times (turn off times) over 25ns can cause bus contention. This does not damage the
parts, but causes an increase in operating current. Specifications assume a 50% duty cycle for the oscillator. Port 2 and ALE timing
changes in relation to duty cycle variation. Some AC timing characteristic drawings contain references to the CLK signal. This
waveform is provided to assist in determining the relative occurrence of events and cannot be used to determine the timing of
signals relative to the external clock. AC timing is characterized and guaranteed by design but is not production tested.
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