MT9094AP 查看數據表（PDF） - Zarlink Semiconductor Inc
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MT9094AP Datasheet PDF : 37 Pages
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MT9094
Data Sheet
SERIAL
PORT
DSP GAIN*
PCM
Receive
–72 to
+22.5 dB
(1.5dB
steps)
DTMF,
Tone
Ringer &
Handsfree
PCM
–72 to
+22.5 dB
(1.5dB
steps)
Transmit
DIGITAL DOMAIN
FILTER/CODEC
Receive
Filter Gain
0 to –7 dB
(1 dB steps)
Side-tone
–9.96 to
+9.96dB
(3.32 dB steps)
Side-tone
Nominal
Gain
µ-Law –11 dB
Α-Law –18.8 dB
Transmit
Filter Gain
0 to +7dB
(1 dB steps)
TRANSDUCER INTERFACE
µ-Law –6.3 dB
Α-Law –3.7 dB
-6 dB
Receiver
Driver
Speaker
Phone
Driver
0.2dB*
-6 dB
HSPKR+
75
HSPKR–
75
SPKR+
SPKR–
Handset
Receiver
(150Ω)
Speaker Gain
0 to –24 dB
(8 dB steps)
Tone
Ringer
(input
from DSP)
Speakerphone
Speaker
(40Ω nominal)
(32Ω min)
M
Transmit
U
Gain
µ-Law 6.1dB
X
Α-Law 15.4dB
ANALOG DOMAIN
MIC+ Handsfree
MIC– mic
M+ Transmitter
M– microphone
Internal to Device
Note: *gain the same for A-Law and m−Law
Figure 3 - Audio Gain Partitioning
External to Device
On PWRST (pin 6) the Filter/CODEC defaults such that the side-tone path, dial tone filter and 400 Hz transmit filter
are off, all programmable gains are set to 0 dB and µ-Law companding is selected. Further, the Filter/CODEC is
powered down due to the PuFC bit (Transducer Control Register, address 0Eh) being reset. This bit must be set
high to enable the Filter/CODEC.
The internal architecture is fully differential to provide the best possible noise rejection as well as to allow a wide
dynamic range from a single 5 volt supply design. This fully differential architecture is continued into the Transducer
Interface section to provide full chip realization of these capabilities.
A reference voltage (VRef), for the conversion requirements of the CODER section, and a bias voltage (VBias), for
biasing the internal analog sections, are both generated on-chip. VBias is also brought to an external pin so that it
may be used for biasing any external gain plan setting amplifiers. A 0.1 µF capacitor must be connected from VBias
to analog ground at all times. Likewise, although VRef may only be used internally, a 0.1 µF capacitor from the VRef
5
Zarlink Semiconductor Inc.
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