H3LIS331DLTR 查看數據表（PDF） - STMicroelectronics
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H3LIS331DLTR Datasheet PDF : 38 Pages
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H3LIS331DL
Mechanical and electrical specifications
2.3
2.3.1
Communication interface characteristics
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Symbol
Table 5. SPI slave timing values
Parameter
Value (1)
Min.
Max.
Unit
tc(SPC)
SPI clock cycle
100
ns
fc(SPC)
SPI clock frequency
10
MHz
tsu(CS)
CS setup time
6
th(CS)
CS hold time
8
tsu(SI)
SDI input setup time
5
th(SI)
SDI input hold time
15
ns
tv(SO)
SDO valid output time
50
th(SO)
SDO output hold time
9
tdis(SO)
SDO output disable time
50
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not
tested in production.
Figure 3. SPI slave timing diagram (2)
2. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports.
3. When no communication is ongoing, data on CS, SPC, SDI and SDO are driven by internal pull-up resistors.
DocID023111 Rev 3
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