74LV595D(2016) 查看數據表（PDF） - NXP Semiconductors.

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74LV595D
(Rev.:2016)

8-bit serial-in/serial-out or parallel-out shift register; 3-state

NXP Semiconductors. 

Nexperia

74LV595

8-bit serial-in/serial-out or parallel-out shift register; 3-state

9,

6+&3LQSXW

*1'

9,

67&3LQSXW

*1'

92+

4 QRXWSXW



92/

90

WVX

90

W:

W 3/+

90

 IPD[

W 3+/

PQD

Fig 9.

Measurement points are given in Table 8.

VOL and VOH are typical output voltage drops that occur with the output load.

The storage clock (STCP) to parallel data output (Qn) propagation delays, the storage clock pulse width

and the shift clock to storage clock set-up time

9,

6+&3LQSXW

*1'

9,

'6LQSXW

*1'

90

W VX

WK

90

W VX

WK

92+

4 6RXWSXW

92/

90

PQD

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

VOL and VOH are typical output voltage drops that occur with the output load.

Fig 10. The data set-up and hold times for the serial data input (DS)

74LV595

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4 — 18 March 2016

© Nexperia B.V. 2017. All rights reserved

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