AD7657(RevPrl) 查看數據表（PDF） - Analog Devices
零件编号
产品描述 (功能)
比赛名单
AD7657
(Rev.:RevPrl)
(Rev.:RevPrl)
Analog Devices
AD7657 Datasheet PDF : 25 Pages
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Preliminary Technical Data
AD7658/AD7657/AD7656
TIMING SPECIFICATIONS1
Table 4. AVCC = 4.5 V to 5.5 V, VDD = 9.5 V to 16.5 V, VSS = -9.5 V to -16.5V, VDRIVE = 2.7V to 5.25V; TA = TMIN to TMAX, unless
otherwise noted
Limit at TMIN, TMAX
Parameter 5 V
Unit
Description
Parallel Mode
tCONVERT
3
tQUIET
400
t1
3
Twake-up
TBD
Write Operation
t13
0
t14
0
t12
20
t15
5
t12/14/16
5
Read Operation
t2
0
t3
0
t4
0
t5
30
t6
30
t7
15
25
t9
20
Serial Interface
µs typ
ns min
ns min
ns typ
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
Conversion Time, Internal Clock
Minimum quiet time required between bus relinquish and start of next conversion
CONVST high to BUSY high
STBY rising edge to CONVST rising edge
CS to WR setup time
CS to WR Hold time
WR Pulse width
Data setup time before WR rising edge
Data hold after WR rising edge
BUSY to RD Delay
CS to RD setup time
CS to RD Hold time
RD Pulse width
Data access time after RD falling edge
Bus relinquish time after RD rising edge
Minimum time between reads
fSCLK
20
MHz max Frequency of Serial Read Clock
t17
10
ns max
CS to SCLK setup time
t18
15
ns max Delay from CS until SDATA three-state disabled
t19
20
ns max Data access time after SCLK rising edge
t20
0.4 tSCLK ns min
SCLK low pulse width
t21
0.4 tSCLK ns min
SCLK high pulse width
t22
5
ns min SCLK to data valid hold time
t23
30
ns max CS rising edge to SDATA high impedance
200µA
IOL
TO OUTPUT
PIN CL
50pF
200µA
IOH
1.6V
Figure 2. Load Circuit for Digital Output Timing Specification
1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
Rev. PrI | Page 9 of 25
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