H27UBG8T2BTA 查看數據表（PDF） - Hynix Semiconductor

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H27UBG8T2BTA

32Gb(4096M x 8bit) Legacy MLC NAND Flash

Hynix Semiconductor 

Preliminary

H27UBG8T2BTR-BC Series

32Gb(4096M x 8bit) Legacy MLC NAND Flash

1.2. Pin Descriptions

Pin Name

I/O 0―

I/O 7

Description

DATA INPUTS/OUTPUTS

The I/O pins is used to COMMAND LATCH cycle, ADDRESS INPUT cycle, and DATA in-out

cycles during read / write operations. The I/O pins float to High-Z when the device is

deselected or the outputs are disabled.

COMMAND LATCH ENABLE

CLE

This input activates the latching of the I/O inputs inside the Command Register on the Rising

edge of Write Enable (WE#).

ALE

CE#

WE#

ADDRESS LATCH ENABLE

This input activates the latching of the I/O inputs inside the Address Register on the Rising

edge of Write Enable (WE#).

CHIP ENABLE

This input controls the selection of the device. When the device is busy, CE# low does not

deselect the memory. The device goes into Stand-by mode when CE# goes High during the

device is in Ready state. The CE# signal is ignored when device is in Busy state, and will not

enter Standby mode even if the CE# goes high.

WRITE ENABLE

This input acts as clock to latch Command, Address and Data. The I/O inputs are latched on

the rise edge of WE#.

RE#

WP#

R/B#

VCCQ

VSSQ

VCC

VSS

NC

READ ENABLE

The RE# input is the serial data-out control, and when active drives the data onto the I/O

bus. Data is valid tREA after the falling edge of RE# which also increments the internal

column address counter by one.

WRITE PROTECT

The WP# pin, when Low, provides a hardware protection against undesired write operations.

Hardware Write Protection is activated when the Write Protect pin is low. In this condition

modify operation do not start and the content of the memory is not altered. Write Protect pin

is not latched by Write Enable to ensure the protection even during the power up phases.

READY / BUSY

The Ready/Busy output is an Open Drain pin that signals the state of the memory.

SUPPLY VOLTAGE FOR I/O BUFFER

GROUND FOR I/O BUFFER

SUPPLY VOLTAGE

The VCC supplies the power for all the operations. (Read, Write, and Erase).

GROUND

NO CONNECTED

Table 2 : Signal descriptions

NOTE: A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground

pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to

carry the currents required during program and erase operations.

Rev 0.7 / Jan. 2011

7

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