IC61LV25616-15B 查看數據表（PDF） - Integrated Circuit Solution Inc

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IC61LV25616-15B

256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY

Integrated Circuit Solution Inc 

IC61LV25616

AC WAVEFORMS

WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3)

ADDRESS

t WC

ADDRESS 1

t WC

ADDRESS 2

OE

t SA

CE LOW

WE

UB, LB

DOUT

DIN

t PWB

t HZWE

DATA UNDEFINED

WORD 1

HIGH-Z

t SD

DATAIN

VALID

t HA

t SA

t PWB

WORD 2

t HA

t LZWE

t HD

t SD

DATAIN

VALID

t HD

Notes:

1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be

in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is

referenced to the rising or falling edge of the signal that terminates the Write.

2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.

3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.

10

Integrated Circuit Solution Inc.

AHSR022-0A 09/11/2001

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