HD74HC165DP 查看數據表（PDF） - Hitachi -> Renesas Electronics
零件编号
产品描述 (功能)
比赛名单
HD74HC165DP Datasheet PDF : 9 Pages
| |||
HD74HC165
Parallel-load 8-bit Shift Register
Description
This 8-bit serial shift register shifts data from QA to QH when clocked. Parallel inputs to each stage are
enabled by a low level at the Shift/Load input. Also included is a gated clock input and a complementary
output from the eighth bit.
Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a clock inhibit
function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with
the Shift/Load input high enables the other clock input. Data transfer occurs on the positive going edge of
the clock. Parallel loading is inhibited as long as the Shift/Load input is high. When taken low, data at the
parallel inputs is loaded directly into the register independent of the state of the clock.
Features
• High Speed Operation: tpd (Clock to QH) = 21 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
Inputs
Shift/Load
L
H
H
H
H
Clock Inhibit
X
L
L
L
H
Clock
X
L
X
Parallel
Serial A ······ H
X
a ······h
X
X
H
X
L
X
X
X
Internal outputs
QA
QB
a
b
QA0
H
QB0
QAn
L
QAn
QA0
QB0
Output
QH
h
QH0
QGn
QGn
QH0
Share Link: 