WT6148 查看數據表（PDF） - Weltrend Semiconductor
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WT6148 Datasheet PDF : 5 Pages
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WT6148/WT6160v1.02
Digital Monitor Controller
43 - - - NC
44 44 42 - NC
No Connection.
No Connection.
FUNCTIONAL DESCRIPTION
CPU
8-bit 6502 compatible CPU operates at 6MHz. Address bus is 16-bit and data bus is 8-bit.
The non-maskable interrupt (/NMI) of 6502 is modified to be maskable and is defined as INT0 with higher
priority. The interrupt request (/IRQ) of 6502 is defined as INT1 with lower priority.
Please refer the 6502 reference menu for more detail.
RAM
The 1024 bytes SRAM include :
128 bytes SRAM are from $0080H to $00FFH
256 bytes SRAM are from $0100H to $01FFH
256 bytes SRAM are from $0200H to $02FFH
256 bytes SRAM are from $0300H to $03FFH
128 bytes SRAM are from $0400H to $047FH
The 32 bytes SRAM bit addressible are from $0500H to $05FFH
ROM
For WT6148, ROM address is located from $4000h to $FFFFh.
For WT6160, ROM address is located from $1000h to $FFFFh.
The following addresses are reserved for special purpose :
$FFFAh (low byte) and $FFFBh (high byte) : INT0 interrupt vector.
$FFFCh (low byte) and $FFFDh (high byte) : program reset interrupt vector.
$FFFEh (low byte) and $FFFFh (high byte) : INT1 interrupt vector.
Weltrend Semiconductor, Inc.
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