MT6305B 查看數據表（PDF） - MediaTek Inc

零件编号

产品描述 (功能)

比赛名单

MT6305B

GSM Power Management System

MediaTek Inc 

Confidential Information

MT6305B

Applications Information

External Components Selection

Input Capacitor Selection

For each of input pins (V BAT) of MT6305, a local by-

pass capacitor is recommended. Use a 10µF, low ESR

capacitor. MLCC capacitors provide the best combina-

tion of low ESR and small size. Using a 10µF Tantalum

capacitor with a small (1µF or 2.2µF) ceramic in parallel

is an alternative low cost solution.

For charger input pin (CHRIN), a bypass 1µF ceramic

capacitor is recommended.

LDO Capacitor Selection

The digital core, analog, memory LDOs require a 4.7µF

capacitor, the digital IO, SIM TCXO LDOs require a 1µF

capacitor and the, RTC LDO require a 0.22µF capacitor.

Large value capacitor may be used for desired noise or

PSRR issue. But take consideration of the settling time

that is acceptable for system application. The MLCC

X5R type capacitors must be used with VTCXO and VA

LDOs for good system performance. For other LDOs,

MLCC X5R type capacitors are also recommended to

use.

RESET Capacitor Selection

RESET is held low at power-up until a delay time when

LDOs are up. The delay is set by an external capacitor

on RESCAP pin. It can be determinated by the Eq.(1).

A 100nF capacitor will produce a 200ms delay.

Setting the Charge Current

MT6305 is capable of charging battery. The charging

current is programmed with an external sense resistor,

Rsen. It is calculated as the Eq.(3). If the charge current

is defined, Rsen can be found.

Appropriate sense resistors are available from the fol-

lowing vendors: Vishay Dale, IRC, Panasonic.

Figure 4. Top Layer of reference PCB Layout

Charger FET Selection

The PMOS FET selection of charger should considerate

the minimum drain-source breakdown voltage (BVDS),

the minimum turn-on threshold voltage (VGS), and cur-

rent-handling and power-dissipation qualities.

These specifications can be calculated as below:

V GS = VCHRIN - V GATEDRV

V DS = VCHRIN - VDIODE - V SENSE- VBAT

RDS(ON) =

VDS

ICHR

P DISS = ( VCHRIN-VDIODE-V SENSE-VBAT) x ICHR

Appropriate PMOS FETs are available from the follow-

ing vendors: Siliconix, IR, Fairchild.

Charger Diode Selection

The diode shown in Figure 3is used to prevent the bat-

tery from discharging through the PMOS’s body diode

into the charger’s internal circuits. Choose a diode with

a current rating high enough to handle the battery

charging current and a voltage rating greater than Vbat.

La yout Guideline

Use the following general guild-line when designing

printed circuit boards:

1. Split battery connection to the VBAT, AVBAT pins of

MT6305. Locate the input capacitor as close to the

pins as possible.

2. Va and Vtcxo capacitors should be returned to

AGND.

3. Split the ground connection. Use separate traces or

planes for the analog, digital, and power grounds (i.e.

AGND, DGND, PGND pins of MT6305, respectively)

and tie them together at a single point, preferably

close to battery return.

4. Run a separate trace from the BATSNS pin to the

battery to prevent voltage drop error in the measure-

ment.

5. Kelvin-connect the charge current sense resistor by

running separate traces to the BATSNS and ISENSE

pins. Make sure that the traces are terminated as

close to the resistor’s body as possible.

6. Careful use of copper area, weight, and multi-layer

constructibon will contribute to improve thermal per-

formance.

7. See Fig4. for reference PCB layout. The thermal

pad is attached to die substrate, so the thermal

planes that the vias attach the package toMust be

connected to GND.

MediaTek Confidential

Revision 1.1–Apr. 22, 2005

© 2002 MediaTek Inc.

The information contained in this document can be modified without notice

Page 29 of 33

Share Link: