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ADUM4470

Isolated Switching Regulator with Quad-Channel Isolators

Analog Devices 

Data Sheet

ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474

Parameter

Logic High Output Voltages

Logic Low Output Voltages

AC SPECIFICATIONS

ADuM447xARIZ

Minimum Pulse Width

Maximum Data Rate

Propagation Delay

Pulse Width Distortion, |tPLH − tPHL|

Propagation Delay Skew

Channel-to-Channel Matching

ADuM447xCRIZ

Minimum Pulse Width

Maximum Data Rate

Propagation Delay

Pulse Width Distortion, |tPLH − tPHL|

Change vs. Temperature

Propagation Delay Skew

Channel-to-Channel Matching,

Codirectional Channels

Channel-to-Channel Matching,

Opposing Directional Channels

Output Rise/Fall Time (10% to 90%)

Common-Mode Transient Immunity

at Logic High Output

Common-Mode Transient Immunity

at Logic Low Output

Refresh Rate

Symbol

VOAH, VOBH,

VOCH, VODH

VOAL, VOBL,

VOCL, VODL

Min

VDDA − 0.3,

VISO − 0.3

VDDA − 0.5,

VISO − 0.5

PW

1

tPLH, tPHL

PWD

tPSK

tPSKCD/tPSKOD

PW

25

tPLH, tPHL

30

PWD

tPSK

tPSKCD

tPSKCD

tR/tF

|CMH|

25

|CML|

25

fr

Typ

Max Unit

5.0

V

4.8

V

0.0

0.1 V

0.0

0.4 V

Test Conditions/Comments

IOx = −20 µA, VIx = VIxH

IOx = −4 mA, VIx = VIxH

IOx = 20 µA, VIx = VIxH

IOx = 4 mA, VIx = VIxH

1000 ns

CL = 15 pF, CMOS signal levels

Mbps CL = 15 pF, CMOS signal levels

55

100 ns

CL = 15 pF, CMOS signal levels

40

ns

CL = 15 pF, CMOS signal levels

50

ns

CL = 15 pF, CMOS signal levels

50

ns

CL = 15 pF, CMOS signal levels

40

ns

CL = 15 pF, CMOS signal levels

Mbps CL = 15 pF, CMOS signal levels

45

60

ns

CL = 15 pF, CMOS signal levels

6

ns

CL = 15 pF, CMOS signal levels

5

ps/°C

CL = 15 pF, CMOS signal levels

15

ns

CL = 15 pF, CMOS signal levels

6

ns

CL = 15 pF, CMOS signal levels

15

ns

CL = 15 pF, CMOS signal levels

2.5

ns

CL = 15 pF, CMOS signal levels

35

kV/µs

VIx = VDDA or VISO, VCM = 1000 V,

transient magnitude = 800 V

35

kV/µs

VIx = 0 V or VISO, VCM = 1000 V,

transient magnitude = 800 V

1.0

Mbps

1 VDD1 is the power supply for the push-pull transformer.

2 VDDA is the power supply of Side 1 of the ADuM447x.

3 The contributions of supply current values for all four channels are combined at identical data rates.

4 The VISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current

proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the

Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the VISO power budget.

5 The power demands of the quiescent operation of the data channels were not separated from the power supply section. Efficiency includes the quiescent power

consumed by the I/O channels as part of the internal power consumption.

6 This current is available for driving external loads at the VISO output. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load

representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of available current at less than the maximum data rate.

Rev. 0 | Page 5 of 36

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