HD74LS160AFPEL 查看數據表（PDF） - Renesas Electronics
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HD74LS160AFPEL Datasheet PDF : 11 Pages
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HD74LS160A
Testing Table
Inputs
Item
From input to
output
Clear Load
Enable
Clock
Data
P
T
A
B
C
D
ƒmax
4.5V 4.5V 4.5V 4.5V
IN
GND GND GND GND
CK Ripply
→ Carry
4.5V 4.5V 4.5V 4.5V
IN
GND GND GND GND
CK → Q
4.5V 4.5V 4.5V 4.5V
IN
tPLH
tPHL
CK → Q
Enable
T
→
Ripple
Carry
4.5V
4.5V
GND
GND
GND
4.5V
GND
IN
IN
IN**
GND
IN*
4.5V
GND
IN*
GND
GND
IN*
GND
GND
IN*
4.5V
CLR → Q
IN GND GND GND IN**
4.5V
4.5V
4.5V
4.5V
Notes: * Measuring outputs correspond to this condition, each outputs (QA, QB, QC, and QD) must not be over the
following rate, “H”, “L”, “L”, and “H”.
** For initialized
Item From input to output
ƒmax
CK→Ripple Carry
CK→Q
tPLH CK→Q
tPHL Enable T→Ripple Carry
CLR→Q
QA
OUT
—
OUT
OUT
—
OUT
QB
OUT
—
OUT
OUT
—
OUT
Outputs
QC
OUT
—
OUT
OUT
—
OUT
QD
OUT
—
OUT
OUT
—
OUT
Ripple Carry
OUT
OUT
—
—
OUT
—
Rev.3.00, Jul.15.2005, page 6 of 10
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